diff options
Diffstat (limited to 'test')
27 files changed, 213 insertions, 213 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index cb63cacf..7922c278 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -17,12 +17,12 @@ circuit top : ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := a$0$x ; CHECK: node b$x#0 = i - ; CHECK: when eq-uu(b$x#0, UInt(1)) : + ; CHECK: when eq(b$x#0, UInt(1)) : ; CHECK: b$x := a$1$x ; CHECK: node b$y#0 = i - ; CHECK: when eq-uu(b$y#0, UInt(0)) : + ; CHECK: when eq(b$y#0, UInt(0)) : ; CHECK: a$0$y := b$y - ; CHECK: when eq-uu(b$y#0, UInt(1)) : + ; CHECK: when eq(b$y#0, UInt(1)) : ; CHECK: a$1$y := b$y j := b.x diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index c359d871..4f8c31e2 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -15,11 +15,11 @@ circuit top : r.y := b on-reset r := w -; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1)) +; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1)) ; CHECK: r$y := Register(b, UInt(1)) ; CHECK: a := UInt(1) ; CHECK: b := UInt(2) ; CHECK: w$x := b -; CHECK: w$y := mux-uu(reset, r$y, a) +; CHECK: w$y := mux(reset, r$y, a) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index 2e8cc82a..f7ac8337 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -20,5 +20,5 @@ circuit top : on-reset r := y r := b r := z -; CHECK: r := Register(mux-uu(reset, mux-uu(q, y, mux-uu(p, x, w)), z), UInt(1)) +; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1)) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index e209d94f..b71a5d50 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -7,6 +7,6 @@ circuit top : reg r : UInt on-reset r := UInt(10) r := UInt(20) -; CHECK: r := Register(mux-uu(reset, UInt(10), UInt(20)), mux-uu(reset, UInt(1), p)) +; CHECK: r := Register(mux(reset, UInt(10), UInt(20)), mux(reset, UInt(1), p)) ; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 23d92b4f..6bceda5c 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -7,7 +7,7 @@ circuit top : input y : UInt output z : UInt z := sub-wrap(x, y) - ;CHECK: z@<t:UInt> := sub-wrap-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> + ;CHECK: z@<t:UInt> := sub-wrap(x@<t:UInt>, y@<t:UInt>)@<t:UInt> module gcd : input a : UInt<16> input b : UInt<16> @@ -20,7 +20,7 @@ circuit top : on-reset x := UInt(0) on-reset y := UInt(42) when gt(x, y) : - ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : + ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : inst s of subtracter ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>, z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}> s.x := x @@ -39,7 +39,7 @@ circuit top : x := a y := b v := eq(v, UInt(0)) - ;CHECK: v@<t:UInt> := eq-uu(v@<t:UInt>, UInt(0))@<t:UInt> + ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt(0))@<t:UInt> z := x module top : input a : UInt<16> diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index e0022cfb..05e9adf8 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -9,131 +9,131 @@ circuit top : wire d : SInt<8> wire e : UInt<1> - node vadd = add(a, c) ;CHECK: node vadd = add-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xadd-us = add-us(a, d) ;CHECK: node xadd-us = add-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yadd-su = add-su(c, b) ;CHECK: node yadd-su = add-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zadd-ss = add-ss(c, d) ;CHECK: node zadd-ss = add-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsub = sub(a, c) ;CHECK: node vsub = sub-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsub-uu = sub-uu(a, b) ;CHECK: node wsub-uu = sub-uu(a@<t:UInt>, b@<t:UInt>)@<t:SInt> - node xsub-us = sub-us(a, d) ;CHECK: node xsub-us = sub-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysub-su = sub-su(c, b) ;CHECK: node ysub-su = sub-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsub-ss = sub-ss(c, d) ;CHECK: node zsub-ss = sub-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vmul = mul(a, c) ;CHECK: node vmul = mul-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wmul-uu = mul-uu(a, b) ;CHECK: node wmul-uu = mul-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmul-us = mul-us(a, d) ;CHECK: node xmul-us = mul-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ymul-su = mul-su(c, b) ;CHECK: node ymul-su = mul-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmul-ss = mul-ss(c, d) ;CHECK: node zmul-ss = mul-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vdiv = div(a, c) ;CHECK: node vdiv = div-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wdiv-uu = div-uu(a, b) ;CHECK: node wdiv-uu = div-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xdiv-us = div-us(a, d) ;CHECK: node xdiv-us = div-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ydiv-su = div-su(c, b) ;CHECK: node ydiv-su = div-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zdiv-ss = div-ss(c, d) ;CHECK: node zdiv-ss = div-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vmod = mod(a, c) ;CHECK: node vmod = mod-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wmod-uu = mod-uu(a, b) ;CHECK: node wmod-uu = mod-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmod-us = mod-us(a, d) ;CHECK: node xmod-us = mod-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ymod-su = mod-su(c, b) ;CHECK: node ymod-su = mod-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmod-ss = mod-ss(c, d) ;CHECK: node zmod-ss = mod-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vquo = quo(a, c) ;CHECK: node vquo = quo-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wquo-uu = quo-uu(a, b) ;CHECK: node wquo-uu = quo-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xquo-us = quo-us(a, d) ;CHECK: node xquo-us = quo-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yquo-su = quo-su(c, b) ;CHECK: node yquo-su = quo-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zquo-ss = quo-ss(c, d) ;CHECK: node zquo-ss = quo-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vrem = rem(a, c) ;CHECK: node vrem = rem-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wrem-uu = rem-uu(a, b) ;CHECK: node wrem-uu = rem-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xrem-us = rem-us(a, d) ;CHECK: node xrem-us = rem-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yrem-su = rem-su(c, b) ;CHECK: node yrem-su = rem-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zrem-ss = rem-ss(c, d) ;CHECK: node zrem-ss = rem-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wadd-wrap-uu = add-wrap-uu(a, b) ;CHECK: node wadd-wrap-uu = add-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xadd-wrap-us = add-wrap-us(a, d) ;CHECK: node xadd-wrap-us = add-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yadd-wrap-su = add-wrap-su(c, b) ;CHECK: node yadd-wrap-su = add-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zadd-wrap-ss = add-wrap-ss(c, d) ;CHECK: node zadd-wrap-ss = add-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsub-wrap-uu = sub-wrap-uu(a, b) ;CHECK: node wsub-wrap-uu = sub-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xsub-wrap-us = sub-wrap-us(a, d) ;CHECK: node xsub-wrap-us = sub-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysub-wrap-su = sub-wrap-su(c, b) ;CHECK: node ysub-wrap-su = sub-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsub-wrap-ss = sub-wrap-ss(c, d) ;CHECK: node zsub-wrap-ss = sub-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vlt = lt(a, c) ;CHECK: node vlt = lt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wlt-uu = lt-uu(a, b) ;CHECK: node wlt-uu = lt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xlt-us = lt-us(a, d) ;CHECK: node xlt-us = lt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ylt-su = lt-su(c, b) ;CHECK: node ylt-su = lt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zlt-ss = lt-ss(c, d) ;CHECK: node zlt-ss = lt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vleq = leq(a, c) ;CHECK: node vleq = leq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wleq-uu = leq-uu(a, b) ;CHECK: node wleq-uu = leq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xleq-us = leq-us(a, d) ;CHECK: node xleq-us = leq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yleq-su = leq-su(c, b) ;CHECK: node yleq-su = leq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zleq-ss = leq-ss(c, d) ;CHECK: node zleq-ss = leq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgt = gt(a, c) ;CHECK: node vgt = gt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgt-uu = gt-uu(a, b) ;CHECK: node wgt-uu = gt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgt-us = gt-us(a, d) ;CHECK: node xgt-us = gt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygt-su = gt-su(c, b) ;CHECK: node ygt-su = gt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgt-ss = gt-ss(c, d) ;CHECK: node zgt-ss = gt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgeq = geq(a, c) ;CHECK: node vgeq = geq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgeq-uu = geq-uu(a, b) ;CHECK: node wgeq-uu = geq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgeq-us = geq-us(a, d) ;CHECK: node xgeq-us = geq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygeq-su = geq-su(c, b) ;CHECK: node ygeq-su = geq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgeq-ss = geq-ss(c, d) ;CHECK: node zgeq-ss = geq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vneq = neq(a, b) ;CHECK: node vneq = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node wneq-uu = neq-uu(a, b) ;CHECK: node wneq-uu = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zneq-ss = neq-ss(c, d) ;CHECK: node zneq-ss = neq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node veq = eq(a, b) ;CHECK: node veq = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node weq-uu = eq-uu(a, b) ;CHECK: node weq-uu = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zeq-ss = eq-ss(c, d) ;CHECK: node zeq-ss = eq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vmux = mux(e, a, b) ;CHECK: node vmux = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node wmux-uu = mux-uu(e, a, b) ;CHECK: node wmux-uu = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zmux-ss = mux-ss(e, c, d) ;CHECK: node zmux-ss = mux-ss(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vpad = pad(a, 10) ;CHECK: node vpad = pad-u(a@<t:UInt>, 10)@<t:UInt> - node wpad-u = pad-u(a, 10) ;CHECK: node wpad-u = pad-u(a@<t:UInt>, 10)@<t:UInt> - node zpad-s = pad-s(c, 10) ;CHECK: node zpad-s = pad-s(c@<t:SInt>, 10)@<t:SInt> - - node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt-s(d@<t:SInt>)@<t:UInt> - node was-UInt-u = as-UInt-u(a) ;CHECK: node was-UInt-u = as-UInt-u(a@<t:UInt>)@<t:UInt> - node zas-UInt-s = as-UInt-s(c) ;CHECK: node zas-UInt-s = as-UInt-s(c@<t:SInt>)@<t:UInt> - - node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt-u(a@<t:UInt>)@<t:SInt> - node was-SInt-u = as-SInt-u(a) ;CHECK: node was-SInt-u = as-SInt-u(a@<t:UInt>)@<t:SInt> - node zas-SInt-s = as-SInt-s(c) ;CHECK: node zas-SInt-s = as-SInt-s(c@<t:SInt>)@<t:SInt> - - node vshl = shl(a, 10) ;CHECK: node vshl = shl-u(a@<t:UInt>, 10)@<t:UInt> - node wshl-u = shl-u(a, 10) ;CHECK: node wshl-u = shl-u(a@<t:UInt>, 10)@<t:UInt> - node zshl-s = shl-s(c, 10) ;CHECK: node zshl-s = shl-s(c@<t:SInt>, 10)@<t:SInt> - - node vdshl = dshl(a, a) ;CHECK: node vdshl = dshl-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshl-u = dshl-u(a, a) ;CHECK: node wdshl-u = dshl-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshl-s = dshl-s(c, a) ;CHECK: node zdshl-s = dshl-s(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vdshr = dshr(a, a) ;CHECK: node vdshr = dshr-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshr-u = dshr-u(a, a) ;CHECK: node wdshr-u = dshr-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshr-s = dshr-s(c, a) ;CHECK: node zdshr-s = dshr-s(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vshr = shr(a, 10) ;CHECK: node vshr = shr-u(a@<t:UInt>, 10)@<t:UInt> - node wshr-u = shr-u(a, 10) ;CHECK: node wshr-u = shr-u(a@<t:UInt>, 10)@<t:UInt> - node zshr-s = shr-s(c, 10) ;CHECK: node zshr-s = shr-s(c@<t:SInt>, 10)@<t:SInt> - - node vconvert = convert(a) ;CHECK: node vconvert = convert-u(a@<t:UInt>)@<t:SInt> - node wconvert-u = convert-u(a) ;CHECK: node wconvert-u = convert-u(a@<t:UInt>)@<t:SInt> - node zconvert-s = convert-s(c) ;CHECK: node zconvert-s = convert-s(c@<t:SInt>)@<t:SInt> - - node vneg = neg(a) ;CHECK: node vneg = neg-u(a@<t:UInt>)@<t:UInt> - node wneg-u = neg-u(a) ;CHECK: node wneg-u = neg-u(a@<t:UInt>)@<t:UInt> - node zneg-s = neg-s(c) ;CHECK: node zneg-s = neg-s(c@<t:SInt>)@<t:UInt> + node vadd = add(a, c) ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xadd = add(a, d) ;CHECK: node xadd = add(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yadd = add(c, b) ;CHECK: node yadd = add(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zadd = add(c, d) ;CHECK: node zadd = add(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vsub = sub(a, c) ;CHECK: node vsub = sub(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wsub = sub(a, b) ;CHECK: node wsub = sub(a@<t:UInt>, b@<t:UInt>)@<t:SInt> + node xsub = sub(a, d) ;CHECK: node xsub = sub(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ysub = sub(c, b) ;CHECK: node ysub = sub(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zsub = sub(c, d) ;CHECK: node zsub = sub(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vmul = mul(a, c) ;CHECK: node vmul = mul(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wmul = mul(a, b) ;CHECK: node wmul = mul(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xmul = mul(a, d) ;CHECK: node xmul = mul(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ymul = mul(c, b) ;CHECK: node ymul = mul(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zmul = mul(c, d) ;CHECK: node zmul = mul(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vdiv = div(a, c) ;CHECK: node vdiv = div(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wdiv = div(a, b) ;CHECK: node wdiv = div(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xdiv = div(a, d) ;CHECK: node xdiv = div(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ydiv = div(c, b) ;CHECK: node ydiv = div(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zdiv = div(c, d) ;CHECK: node zdiv = div(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vmod = mod(a, c) ;CHECK: node vmod = mod(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wmod = mod(a, b) ;CHECK: node wmod = mod(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xmod = mod(a, d) ;CHECK: node xmod = mod(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ymod = mod(c, b) ;CHECK: node ymod = mod(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zmod = mod(c, d) ;CHECK: node zmod = mod(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vquo = quo(a, c) ;CHECK: node vquo = quo(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wquo = quo(a, b) ;CHECK: node wquo = quo(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xquo = quo(a, d) ;CHECK: node xquo = quo(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yquo = quo(c, b) ;CHECK: node yquo = quo(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zquo = quo(c, d) ;CHECK: node zquo = quo(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vrem = rem(a, c) ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wrem = rem(a, b) ;CHECK: node wrem = rem(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wadd-wrap = add-wrap(a, b) ;CHECK: node wadd-wrap = add-wrap(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xadd-wrap = add-wrap(a, d) ;CHECK: node xadd-wrap = add-wrap(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yadd-wrap = add-wrap(c, b) ;CHECK: node yadd-wrap = add-wrap(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zadd-wrap = add-wrap(c, d) ;CHECK: node zadd-wrap = add-wrap(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wsub-wrap = sub-wrap(a, b) ;CHECK: node wsub-wrap = sub-wrap(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xsub-wrap = sub-wrap(a, d) ;CHECK: node xsub-wrap = sub-wrap(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ysub-wrap = sub-wrap(c, b) ;CHECK: node ysub-wrap = sub-wrap(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zsub-wrap = sub-wrap(c, d) ;CHECK: node zsub-wrap = sub-wrap(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vlt = lt(a, c) ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xlt = lt(a, d) ;CHECK: node xlt = lt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ylt = lt(c, b) ;CHECK: node ylt = lt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zlt = lt(c, d) ;CHECK: node zlt = lt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vleq = leq(a, c) ;CHECK: node vleq = leq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wleq = leq(a, b) ;CHECK: node wleq = leq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xleq = leq(a, d) ;CHECK: node xleq = leq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node yleq = leq(c, b) ;CHECK: node yleq = leq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zleq = leq(c, d) ;CHECK: node zleq = leq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vgt = gt(a, c) ;CHECK: node vgt = gt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wgt = gt(a, b) ;CHECK: node wgt = gt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xgt = gt(a, d) ;CHECK: node xgt = gt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ygt = gt(c, b) ;CHECK: node ygt = gt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zgt = gt(c, d) ;CHECK: node zgt = gt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vgeq = geq(a, c) ;CHECK: node vgeq = geq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wgeq = geq(a, b) ;CHECK: node wgeq = geq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xgeq = geq(a, d) ;CHECK: node xgeq = geq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ygeq = geq(c, b) ;CHECK: node ygeq = geq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zgeq = geq(c, d) ;CHECK: node zgeq = geq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vneq = neq(a, b) ;CHECK: node vneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wneq = neq(a, b) ;CHECK: node wneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node veq = eq(a, b) ;CHECK: node veq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vmux = mux(e, a, b) ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wmux = mux(e, a, b) ;CHECK: node wmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zmux = mux(e, c, d) ;CHECK: node zmux = mux(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vpad = pad(a, 10) ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt> + node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt> + node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt> + + node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt(d@<t:SInt>)@<t:UInt> + node was-UInt = as-UInt(a) ;CHECK: node was-UInt = as-UInt(a@<t:UInt>)@<t:UInt> + node zas-UInt = as-UInt(c) ;CHECK: node zas-UInt = as-UInt(c@<t:SInt>)@<t:UInt> + + node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt(a@<t:UInt>)@<t:SInt> + node was-SInt = as-SInt(a) ;CHECK: node was-SInt = as-SInt(a@<t:UInt>)@<t:SInt> + node zas-SInt = as-SInt(c) ;CHECK: node zas-SInt = as-SInt(c@<t:SInt>)@<t:SInt> + + node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt> + node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt> + node zshl = shl(c, 10) ;CHECK: node zshl = shl(c@<t:SInt>, 10)@<t:SInt> + + node vdshl = dshl(a, a) ;CHECK: node vdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node wdshl = dshl(a, a) ;CHECK: node wdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node zdshl = dshl(c, a) ;CHECK: node zdshl = dshl(c@<t:SInt>, a@<t:UInt>)@<t:SInt> + + node vdshr = dshr(a, a) ;CHECK: node vdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node wdshr = dshr(a, a) ;CHECK: node wdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node zdshr = dshr(c, a) ;CHECK: node zdshr = dshr(c@<t:SInt>, a@<t:UInt>)@<t:SInt> + + node vshr = shr(a, 10) ;CHECK: node vshr = shr(a@<t:UInt>, 10)@<t:UInt> + node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt> + node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt> + + node vconvert = convert(a) ;CHECK: node vconvert = convert(a@<t:UInt>)@<t:SInt> + node wconvert = convert(a) ;CHECK: node wconvert = convert(a@<t:UInt>)@<t:SInt> + node zconvert = convert(c) ;CHECK: node zconvert = convert(c@<t:SInt>)@<t:SInt> + + node vneg = neg(a) ;CHECK: node vneg = neg(a@<t:UInt>)@<t:UInt> + node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:UInt> + node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:UInt> node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node vor = bit-or(a, b) ;CHECK: node vor = bit-or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 871e7e8b..6b683e56 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -12,10 +12,10 @@ circuit top : wire c : UInt wire d : SInt - a := dshl-u(x,y) - b := dshl-s(z,y) - c := dshr-u(x,y) - d := dshr-s(z,y) + a := dshl(x,y) + b := dshl(z,y) + c := dshr(x,y) + d := dshr(z,y) ; CHECK: wire a : UInt<23> diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 4d4c3575..9e4bf0f5 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 6f3b51c9..590515e7 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -12,7 +12,7 @@ circuit top : wire c : UInt wire z : UInt - z := mux(c,Pad(a,?),Pad(b,?)) + z := mux(c,a,b) diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 418f784b..2c76bc82 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index f15980b3..29663234 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : - module m : + module top : wire i : UInt<2> wire j : UInt<32> diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index a4ba1eab..0b9d9799 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -1,10 +1,10 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : - module q : + module top : wire i : UInt - wire j : UInt + wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] ; CHECK: wire a$0$x : UInt<32> diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 722d569c..c0acfecd 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -1,42 +1,42 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s circuit top : module m : - input a : { x : UInt, flip y: SInt} - output b : { x : UInt, flip y: SInt} - module subtracter : - input c : { x : UInt[5], flip y : { x : UInt[3], flip y : SInt } } - wire a : { x : UInt, flip y : SInt} - wire b : { x : UInt, flip y : SInt} + input a : { x : UInt<5>, flip y: SInt<5>} + output b : { x : UInt<5>, flip y: SInt<5>} + module top : + input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } + wire a : { x : UInt<5>, flip y : SInt<5>} + wire b : { x : UInt<5>, flip y : SInt<5>} a := b inst i of m i.a := a b := i.b - wire d : UInt[5] + wire d : UInt<5>[5] ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a$x : UInt -;CHECK: output a$y : SInt -;CHECK: output b$x : UInt -;CHECK: input b$y : SInt +;CHECK: input a$x : UInt<5> +;CHECK: output a$y : SInt<5> +;CHECK: output b$x : UInt<5> +;CHECK: input b$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: module subtracter : -;CHECK: input c$x$0 : UInt -;CHECK: input c$x$1 : UInt -;CHECK: input c$x$2 : UInt -;CHECK: input c$x$3 : UInt -;CHECK: input c$x$4 : UInt -;CHECK: output c$y$x$0 : UInt -;CHECK: output c$y$x$1 : UInt -;CHECK: output c$y$x$2 : UInt -;CHECK: input c$y$y : SInt +;CHECK: module top : +;CHECK: input c$x$0 : UInt<5> +;CHECK: input c$x$1 : UInt<5> +;CHECK: input c$x$2 : UInt<5> +;CHECK: input c$x$3 : UInt<5> +;CHECK: input c$x$4 : UInt<5> +;CHECK: output c$y$x$0 : UInt<5> +;CHECK: output c$y$x$1 : UInt<5> +;CHECK: output c$y$x$2 : UInt<5> +;CHECK: input c$y$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: wire a$x : UInt -;CHECK: wire a$y : SInt -;CHECK: wire b$x : UInt -;CHECK: wire b$y : SInt +;CHECK: wire a$x : UInt<5> +;CHECK: wire a$y : SInt<5> +;CHECK: wire b$x : UInt<5> +;CHECK: wire b$y : SInt<5> ;CHECK: a$x := b$x ;CHECK: b$y := a$y ;CHECK: inst i of m @@ -45,9 +45,9 @@ circuit top : ;CHECK: a$y := i.a$y ;CHECK: b$x := i.b$x ;CHECK: i.b$y := b$y -;CHECK: wire d$0 : UInt -;CHECK: wire d$1 : UInt -;CHECK: wire d$2 : UInt -;CHECK: wire d$3 : UInt -;CHECK: wire d$4 : UInt +;CHECK: wire d$0 : UInt<5> +;CHECK: wire d$1 : UInt<5> +;CHECK: wire d$2 : UInt<5> +;CHECK: wire d$3 : UInt<5> +;CHECK: wire d$4 : UInt<5> ;CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index 4cd9f0cc..420c3c7c 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cdg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cdg | tee %s.out | FileCheck %s circuit top : module source : diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 95b125f6..b7915c5d 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : - module q : + module top : wire i : UInt wire j : { x : UInt<32>, flip y : UInt<32> } wire k : { x : UInt<32>, y : UInt<32> } diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 918710a5..a3c4f0ae 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir index 5f5f37fb..7fcf0013 100644 --- a/test/passes/lower-to-ground/test.fir +++ b/test/passes/lower-to-ground/test.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p cdt | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cdt | tee %s.out | FileCheck %s ; CHECK: Done! circuit Top : @@ -8,6 +8,6 @@ circuit Top : output this : {out : {valid : UInt<1>, flip ready : UInt<1>}} inst queue of Queue this.out := queue.out - wire w : { x : UInt, flip y : UInt} - wire a : UInt + wire w : { x : UInt<5>, flip y : UInt<5>} + wire a : UInt<5> w.y := a diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir index a255dc33..97d32397 100644 --- a/test/passes/make-explicit-reset/mix-reset.fir +++ b/test/passes/make-explicit-reset/mix-reset.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abc -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s ; CHECK: Make Explicit Reset circuit top : @@ -23,7 +23,7 @@ circuit top : ;CHECK: input reset : UInt<1> input a : UInt<16> input b : UInt<16> - output z : UInt - inst a of A - ;CHECK: a.reset := reset + output z : UInt<1> + inst x of A + ;CHECK: x.reset := reset ;CHECK: Finished Make Explicit Reset diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index caf7d4b3..31314148 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -1,9 +1,9 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : module top : - wire m : UInt<32>[10][10][10] + wire m : UInt<32>[5][5][5] wire i : UInt accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m> accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m> diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir index 56029969..9ca5d16d 100644 --- a/test/passes/resolve-genders/bigenders.fir +++ b/test/passes/resolve-genders/bigenders.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : - module M : + module top : input i : UInt<10> output o : UInt<10> wire w : {x : UInt<10>, flip y : UInt<10>} diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index 9688a71b..1f6b82a5 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 2f7aae73..6fbaad85 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : @@ -7,7 +7,7 @@ circuit top : input y : UInt output z : UInt z := sub-wrap(x, y) - ;CHECK: z@<g:f> := sub-wrap-uu(x@<g:m>, y@<g:m>) + ;CHECK: z@<g:f> := sub-wrap(x@<g:m>, y@<g:m>) module gcd : input a : UInt<16> input b : UInt<16> @@ -20,7 +20,7 @@ circuit top : on-reset x := UInt(0) on-reset y := UInt(42) when gt(x, y) : - ;CHECK: when gt-uu(x@<g:m>, y@<g:m>) : + ;CHECK: when gt(x@<g:m>, y@<g:m>) : inst s of subtracter ;CHECK: inst s of subtracter@<g:m> s.x := x diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index 9bc67c21..993b7cf2 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 6abc411a..383c2a31 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Lower To Ground circuit top : - module M : + module top : wire w : { flip x : UInt<10>} reg r : { flip x : UInt<10>} w := r ; CHECK r$x := w$x diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 10278fdb..341910d4 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcd -p ck | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p ck | tee %s.out | FileCheck %s ; CHECK: Resolve Kinds circuit top : diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 71835204..5af83202 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijklmn -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Split Expressions circuit top : @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index c8f2b268..3d5ea30f 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Flo circuit top : @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> |