6 files changed, 60 insertions, 1 deletions
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
new file mode 100644
index 00000000..b261f0d1
--- /dev/null
+++ b/test/passes/infer-types/gcd.fir
@@ -0,0 +1,46 @@
+; RUN: firrtl %s abcde | tee %s.out | FileCheck %s
+
+;CHECK: Infer Types
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output z : UInt
+      z := sub-mod(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+; CHECK: reg x : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when greater(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.z
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.z
+      when e :
+         x := a
+         y := b
+      v := equal(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
new file mode 100644
index 00000000..fa0f0c90
--- /dev/null
+++ b/test/passes/infer-types/primops.fir
@@ -0,0 +1,8 @@
+; RUN: firrtl %s abcde | tee %s.out | FileCheck %s
+
+;CHECK: Infer Types
+circuit top :
+   module top :
+      wire io : {input x : UInt, output y : UInt}
+      io.x := add(io.x,io.y)
+;CHECK: n:io:{input x : UInt, output y : UInt}.x := add(n:io:{input x : UInt, output y : UInt}.x, n:io:{input x : UInt, output y : UInt}.y)
diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir
index 9d4de49e..4f64b071 100644
--- a/test/passes/initialize-register/begin.fir
+++ b/test/passes/initialize-register/begin.fir
@@ -1,5 +1,6 @@
 ; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
 
+; CHECK: Initialize Registers
          circuit top :
             module top :
                input a : UInt(16)
@@ -12,6 +13,7 @@
 
                reg r2 : UInt
                r2.init := UInt(0)
+; CHECK-NOT:   r2.init := UInt(0)
 ; CHECK:       wire [[R2:gen[0-9]*]] : UInt
 ; CHECK-NOT:   reg:r2 := n:[[R2]]
 ; CHECK:       n:[[R2]] := Null
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
index e4749abe..c563d639 100644
--- a/test/passes/initialize-register/when.fir
+++ b/test/passes/initialize-register/when.fir
@@ -1,5 +1,6 @@
 ; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
-; CHECK: circuit top :
+
+; CHECK: Initialize Registers
          circuit top :
             module top :
                input a : UInt(16)
diff --git a/test/passes/make-explicit-reset/abc.fir b/test/passes/make-explicit-reset/mix-reset.fir
index caed07ab..23a1232a 100644
--- a/test/passes/make-explicit-reset/abc.fir
+++ b/test/passes/make-explicit-reset/mix-reset.fir
@@ -1,5 +1,6 @@
 ; RUN: firrtl %s abc | tee %s.out | FileCheck %s
 
+; CHECK: Make Explicit Reset
 circuit top :
    module A :
       ;CHECK: input reset : UInt(1)
diff --git a/test/passes/resolve-kinds/ab.fir b/test/passes/resolve-kinds/gcd.fir
index e6f28c21..83091f67 100644
--- a/test/passes/resolve-kinds/ab.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -1,5 +1,6 @@
 ; RUN: firrtl %s ab | tee %s.out | FileCheck %s
 
+; CHECK: Resolve Kinds
 circuit top :
    module subtracter :
       input x : UInt