4 files changed, 137 insertions, 3 deletions
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index f98d98da..fcd08ac6 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -3,10 +3,9 @@
 ;CHECK: Infer Widths
 circuit top :
    module top :
-      wire e : UInt
-      wire x : UInt
+      wire e : UInt(30)
       reg y : UInt
-      y := mux-uu(e, UInt(1), equal-uu(gt-uu(x, x), UInt(0)))
+      y := e
    
 
 ; CHECK: Finished Infer Widths
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
new file mode 100644
index 00000000..bf6f87ab
--- /dev/null
+++ b/test/passes/inline/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl %s abcefghipjkl c | tee %s.out | FileCheck %s
+
+;CHECK: Inline Instances
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap-uu(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt-uu(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := equal-uu(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+; CHECK: Finished Inline Instances
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
new file mode 100644
index 00000000..a659aa07
--- /dev/null
+++ b/test/passes/split-exp/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl %s abcefghipjklm c | tee %s.out | FileCheck %s
+
+;CHECK: Split Expressions
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap-uu(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt-uu(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := equal-uu(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+; CHECK: Finished Split Expressions
diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir
new file mode 100644
index 00000000..7a3179bf
--- /dev/null
+++ b/test/passes/to-flo/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl %s abcefghipjklmno cw | tee %s.out | FileCheck %s
+
+;CHECK: Flo
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap-uu(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt-uu(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := equal-uu(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+;CHECK: Done!
+