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-rw-r--r--test/passes/expand-whens/wacc-wdc.fir24
1 files changed, 0 insertions, 24 deletions
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
deleted file mode 100644
index 25fcff17..00000000
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-circuit top :
- module top :
- input clk : Clock
- wire p : UInt
- cmem m : UInt<4>[10], clk
- p <= UInt(1)
- when p :
- write accessor a = m[UInt(3)]
- a <= UInt(2)
-
-; CHECK: Expand Whens
-
-; CHECK: circuit top :
-; CHECK: module top :
-; CHECK: wire p : UInt
-; CHECK: cmem m : UInt<4>[10], clk
-; CHECK: write accessor a = m[UInt("h3")]
-; CHECK: p <= UInt("h1")
-; CHECK: when p : a <= UInt("h2")
-
-; CHECK: Finished Expand Whens
-
-