diff options
Diffstat (limited to 'test/passes/expand-whens/reg-wdc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-wdc.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index a748dcc2..c6439860 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * circuit top : module top : input clk : Clock @@ -16,8 +15,9 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h00000001") -; CHECK-NOT: when p : r := UInt("h00000002") +; CHECK: p := UInt("h1") +; CHECK-NOT: when p : r := UInt("h2") ; CHECK: Finished Expand Whens +; CHECK: Done! |