diff options
Diffstat (limited to 'test/parser')
| -rw-r--r-- | test/parser/bundle.fir | 43 | ||||
| -rw-r--r-- | test/parser/gcd.fir | 52 |
2 files changed, 95 insertions, 0 deletions
diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir new file mode 100644 index 00000000..c9600d10 --- /dev/null +++ b/test/parser/bundle.fir @@ -0,0 +1,43 @@ +; RUN: firrtl -i %s -o %s.out -X HighFIRRTL && cat %s.out | FileCheck %s +circuit top : + module top : + wire z : { x : UInt, flip y: SInt} + z.x := UInt(1) + z.y := SInt(1) + node x = z.x + node y = z.y + wire a : UInt<3>[10] + a[0] := UInt(1) + a[1] := UInt(1) + a[2] := UInt(1) + a[3] := UInt(1) + a[4] := UInt(1) + a[5] := UInt(1) + a[6] := UInt(1) + a[7] := UInt(1) + a[8] := UInt(1) + a[9] := UInt(1) + node b = a[2] + read accessor c = a[UInt(3)] + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire z : { x : UInt, flip y : SInt} +; CHECK: z.x := UInt("h1") +; CHECK: z.y := SInt("h1") +; CHECK: node x = z.x +; CHECK: node y = z.y +; CHECK: wire a : UInt<3>[10] +; CHECK: a[0] := UInt("h1") +; CHECK: a[1] := UInt("h1") +; CHECK: a[2] := UInt("h1") +; CHECK: a[3] := UInt("h1") +; CHECK: a[4] := UInt("h1") +; CHECK: a[5] := UInt("h1") +; CHECK: a[6] := UInt("h1") +; CHECK: a[7] := UInt("h1") +; CHECK: a[8] := UInt("h1") +; CHECK: a[9] := UInt("h1") +; CHECK: node b = a[2] +; CHECK: read accessor c = a[UInt("h3")] + diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir new file mode 100644 index 00000000..3a9317b8 --- /dev/null +++ b/test/parser/gcd.fir @@ -0,0 +1,52 @@ +; RUN: firrtl -i %s -o %s.out -X HighFIRRTL && cat %s.out | FileCheck %s +circuit GCD : + module GCD : + input e : UInt<1> + input clk : Clock + input reset : UInt<1> + output z : UInt<16> + output v : UInt<1> + input a : UInt<16> + input b : UInt<16> + + reg x : UInt<16>,clk,reset + reg y : UInt<16>,clk,reset + node T_17 = gt(x, y) + when T_17 : + node T_18 = subw(x, y) + x := T_18 + else : + node T_19 = subw(y, x) + y := T_19 + when e : + x := a + y := b + z := x + node T_20 = eq(y, UInt<1>(0)) + v := T_20 + +; CHECK: circuit GCD : +; CHECK: module GCD : +; CHECK: input e : UInt<1> +; CHECK: input clk : Clock +; CHECK: input reset : UInt<1> +; CHECK: output z : UInt<16> +; CHECK: output v : UInt<1> +; CHECK: input a : UInt<16> +; CHECK: input b : UInt<16> +; CHECK: reg x : UInt<16>, clk, reset +; CHECK: reg y : UInt<16>, clk, reset +; CHECK: node T_17 = gt(x, y) +; CHECK: when T_17 : +; CHECK: node T_18 = subw(x, y) +; CHECK: x := T_18 +; CHECK: else : +; CHECK: node T_19 = subw(y, x) +; CHECK: y := T_19 +; CHECK: when e : +; CHECK: x := a +; CHECK: y := b +; CHECK: z := x +; CHECK: node T_20 = eq(y, UInt<1>("h0")) +; CHECK: v := T_20 + |