3 files changed, 64 insertions, 0 deletions
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
new file mode 100644
index 00000000..f78ba45b
--- /dev/null
+++ b/test/features/BulkConnect.fir
@@ -0,0 +1,28 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Lower To Ground
+circuit Top : 
+  module Top : 
+    wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>}
+    wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>}
+    a <> b 
+    ; CHECK:     a$w := b$w
+    ; CHECK:     a$x := b$x
+    ; CHECK-NOT: a$y := b$y
+    ; CHECK-NOT: b$y := a$y
+    ; CHECK-NOT: a$z := b$z
+    
+
+    wire c : { x : { y : UInt<1>, z : UInt<1>}}[4]
+    wire d : { x : { y : UInt<1>}}[2]
+    c <> d
+    ; CHECK:     c$0$x$y := d$0$x$y
+    ; CHECK:     c$1$x$y := d$1$x$y
+    ; CHECK-NOT: c$2$x$y := d$2$x$y
+    ; CHECK-NOT: c$3$x$y := d$3$x$y
+    ; CHECK-NOT: c$0$x$z := d$0$x$z
+    ; CHECK-NOT: c$1$x$z := d$1$x$z
+    ; CHECK-NOT: c$2$x$z := d$2$x$z
+    ; CHECK-NOT: c$3$x$z := d$3$x$z
+
+;CHECK: Finished Lower To Ground
+;CHECK: Done!
diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
new file mode 100644
index 00000000..b47b14ab
--- /dev/null
+++ b/test/features/ExModule.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    output z : UInt<4>
+    inst i of BlackBox
+    i.x := UInt(1)
+    i.y := UInt(2)
+    z := i.z
+  exmodule BlackBox :
+    input x : UInt<4>
+    input y : UInt<4>
+    output z : UInt<4>
+
+;CHECK: Done!
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
new file mode 100644
index 00000000..998df8c9
--- /dev/null
+++ b/test/features/SeqMem.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Top : 
+  module Top : 
+    wire i : UInt<5>
+    wire i0 : UInt<5>
+    wire j : UInt<128>
+
+    i0 := UInt(10)
+
+    cmem m-com : UInt<128>[32]
+    accessor r-com = m-com[i]
+    accessor w-com = m-com[i]
+    j := r-com
+    w-com := j
+
+
+    smem m-seq : UInt<128>[32]
+    accessor r-seq = m-seq[i]
+    accessor w-seq = m-seq[i]
+    j := r-seq
+    w-seq := j