1 files changed, 10 insertions, 0 deletions
diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir
new file mode 100644
index 00000000..f28d1e0b
--- /dev/null
+++ b/test/errors/init/Output.fir
@@ -0,0 +1,10 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Reference y is not fully initialized.
+
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    wire y : UInt<1>
+
+    when UInt(0) : 
+      y := UInt(1)