4 files changed, 55 insertions, 17 deletions
diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 5725aa90..62eba530 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -4,5 +4,6 @@
 
 circuit Flip-Mem : 
   module Flip-Mem : 
-    cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10]
-    smem m-s : {x : UInt<3>, flip y : UInt<5>}[10]
+    input clk : Clock
+    cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10], clk
+    smem m-s : {x : UInt<3>, flip y : UInt<5>}[10], clk
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir
new file mode 100644
index 00000000..1d9f7ef6
--- /dev/null
+++ b/test/errors/high-form/RemoveScope.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Top :
+  module Top :
+    wire x : UInt<1>
+    node p = UInt(1)
+    when p :
+       wire x : UInt<1>
+       x := UInt(1)
+       node y = add(x,UInt(1))
+    else :
+       wire x : UInt<1>
+       x := UInt(1)
+       node z = add(x,UInt(1))
+    x := UInt(1)
+    node w = add(x,UInt(1))
diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir
new file mode 100644
index 00000000..f224ce68
--- /dev/null
+++ b/test/errors/high-form/SpecialChars.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Top :
+  module Top :
+    wire x : UInt<1>
+    x := UInt(1)
+    wire x~y : UInt<2>
+    x~y := UInt(1)
+    wire x!y : UInt<2>
+    x!y := UInt(1)
+    wire x@y : UInt<2>
+    x@y := UInt(1)
+    wire x#y : UInt<2>
+    x#y := UInt(1)
+    wire x%y : UInt<2>
+    x%y := UInt(1)
+    wire x^y : UInt<2>
+    x^y := UInt(1)
+    wire x*y : UInt<2>
+    x*y := UInt(1)
+    wire x-y : UInt<2>
+    x-y := UInt(1)
+    wire x_y : UInt<2>
+    x_y := UInt(1)
+    wire x+y : UInt<2>
+    x+y := UInt(1)
+    wire x=y : UInt<2>
+    x=y := UInt(1)
+    wire x?y : UInt<2>
+    x?y := UInt(1)
+    wire x/y : UInt<2>
+    x/y := UInt(1)
+
+
diff --git a/test/errors/high-form/WrongReset.fir b/test/errors/high-form/WrongReset.fir
deleted file mode 100644
index adeadee6..00000000
--- a/test/errors/high-form/WrongReset.fir
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-
-; CHECK: Module Top has a reset that is not of type UInt<1>.
-; CHECK: Module B has a reset that is not of type UInt<1>.
-; CHECK: Module C has a reset that is not of type UInt<1>.
-
-circuit Top :
-  module Top :
-    input reset : SInt<1>
-  module B :
-    input reset : UInt
-  module C :
-    output reset : UInt<1>
-
-