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-rw-r--r--test/errors/high-form/Flip-Mem.fir6
-rw-r--r--test/errors/high-form/NegVecSize.fir7
-rw-r--r--test/errors/high-form/NegWidth.fir7
-rw-r--r--test/errors/high-form/NumArgs.fir11
4 files changed, 29 insertions, 2 deletions
diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 662fc6f1..5725aa90 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -1,6 +1,8 @@
; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-; CHECK: Memory m cannot be a bundle type with flips.
+; CHECK: Memory m-c cannot be a bundle type with flips.
+; CHECK: Memory m-s cannot be a bundle type with flips.
circuit Flip-Mem :
module Flip-Mem :
- mem m : {x : UInt<3>, flip y : UInt<5>}[10]
+ cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10]
+ smem m-s : {x : UInt<3>, flip y : UInt<5>}[10]
diff --git a/test/errors/high-form/NegVecSize.fir b/test/errors/high-form/NegVecSize.fir
new file mode 100644
index 00000000..16fae565
--- /dev/null
+++ b/test/errors/high-form/NegVecSize.fir
@@ -0,0 +1,7 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Vector type size cannot be negative
+
+circuit Top :
+ module Top :
+ wire x : UInt<3>[-5]
+
diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir
new file mode 100644
index 00000000..3f305301
--- /dev/null
+++ b/test/errors/high-form/NegWidth.fir
@@ -0,0 +1,7 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Width cannot be negative.
+
+circuit Top :
+ module Top :
+ wire x : UInt<-3>
+
diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir
new file mode 100644
index 00000000..4dc8ad46
--- /dev/null
+++ b/test/errors/high-form/NumArgs.fir
@@ -0,0 +1,11 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Primop mux requires 3 expression arguments.
+; CHECK: Primop add requires 2 expression arguments.
+; CHECK: Primop bits requires 2 integer arguments.
+
+circuit Top :
+ module Top :
+ node x = mux(UInt(1),UInt(1))
+ node y = add(SInt(1),UInt(1),UInt(1))
+ node z = bits(UInt(1),1,2,3)
+