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-rw-r--r--test/chisel3/Tbl.fir16
1 files changed, 16 insertions, 0 deletions
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
new file mode 100644
index 00000000..273047b0
--- /dev/null
+++ b/test/chisel3/Tbl.fir
@@ -0,0 +1,16 @@
+circuit Tbl :
+ module Tbl :
+ output o : UInt(16)
+ input i : UInt(16)
+ input d : UInt(16)
+ input we : UInt(1)
+
+ mem m : UInt(10)[256]
+ node T_13 : UInt(1) = UInt(0, 1)
+ o := T_13
+ when we :
+ accessor T_14 = m[i]
+ T_14 := d
+ else :
+ accessor T_15 = m[i]
+ o := T_15 \ No newline at end of file