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-rw-r--r--test/chisel3/EnableShiftRegister.fir23
1 files changed, 0 insertions, 23 deletions
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir
deleted file mode 100644
index bfc8f9c3..00000000
--- a/test/chisel3/EnableShiftRegister.fir
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-
-circuit EnableShiftRegister :
- module EnableShiftRegister :
- input in : UInt<4>
- output out : UInt<4>
- input shift : UInt<1>
-
- reg r0 : UInt<4>
- on-reset r0 := UInt<4>(0)
- reg r1 : UInt<4>
- on-reset r1 := UInt<4>(0)
- reg r2 : UInt<4>
- on-reset r2 := UInt<4>(0)
- reg r3 : UInt<4>
- on-reset r3 := UInt<4>(0)
- when shift :
- r0 := in
- r1 := r0
- r2 := r1
- r3 := r2
- out := r3