diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/ZeroWidth.scala | 5 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ZeroWidthTests.scala | 17 |
2 files changed, 20 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala index 60439ec1..e918ff63 100644 --- a/src/main/scala/firrtl/passes/ZeroWidth.scala +++ b/src/main/scala/firrtl/passes/ZeroWidth.scala @@ -135,8 +135,9 @@ object ZeroWidth extends Transform with DependencyAPIMigration { } } nonZeros match { - case Nil => UIntLiteral(ZERO, IntWidth(BigInt(1))) - case Seq(x) => x + case Nil => UIntLiteral(ZERO, IntWidth(BigInt(1))) + // We may have an SInt, Cat has type UInt so cast + case Seq(x) => castRhs(tpe, x) case seq => DoPrim(Cat, seq, consts, tpe).map(onExp) } case DoPrim(Andr, Seq(x), _, _) if (bitWidth(x.tpe) == 0) => UIntLiteral(1) // nothing false diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala index 99ebbdd3..df630065 100644 --- a/src/test/scala/firrtlTests/ZeroWidthTests.scala +++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala @@ -220,6 +220,23 @@ class ZeroWidthTests extends FirrtlFlatSpec { | x <= UInt<1>(1)""".stripMargin (parse(exec(input))) should be(parse(check)) } + + "Cat of SInt with zero-width" should "keep type correctly" in { + val input = + """circuit Top : + | module Top : + | input x : SInt<0> + | input y : SInt<1> + | output z : UInt<1> + | z <= cat(y, x)""".stripMargin + val check = + """circuit Top : + | module Top : + | input y : SInt<1> + | output z : UInt<1> + | z <= asUInt(y)""".stripMargin + (parse(exec(input))) should be(parse(check)) + } } class ZeroWidthVerilog extends FirrtlFlatSpec { |