diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index aa3eeace..c0fa78f0 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -91,7 +91,8 @@ object VerilogCompiler extends Compiler { def run(c: Circuit, w: Writer) { val loweredIR = PassUtils.executePasses(c, passes) - VerilogEmitter.run(loweredIR, w) + val verilogEmitter = new VerilogEmitter + verilogEmitter.run(loweredIR, w) } } diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 2aee699d..79b1847d 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -54,7 +54,7 @@ object FIRRTLEmitter extends Emitter { case class VIndent() case class VRandom() -object VerilogEmitter extends Emitter { +class VerilogEmitter extends Emitter { val tab = " " val ran = VRandom() var w:Option[Writer] = None |