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-rw-r--r--src/main/scala/firrtl/Emitter.scala45
-rw-r--r--src/main/scala/firrtl/passes/RemoveValidIf.scala2
-rw-r--r--src/test/scala/firrtlTests/AttachSpec.scala30
-rw-r--r--src/test/scala/firrtlTests/CompilerTests.scala51
4 files changed, 62 insertions, 66 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index edeb938d..094815ff 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -363,9 +363,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
case sx: Connect =>
netlist(sx.loc) = sx.expr
sx
- case sx: IsInvalid =>
- netlist(sx.expr) = wref(namespace.newTemp, sx.expr.tpe)
- sx
+ case sx: IsInvalid => error("Should have removed these!")
case sx: DefNode =>
val e = WRef(sx.name, sx.value.tpe, NodeKind, MALE)
netlist(e) = sx.value
@@ -564,15 +562,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
update_and_reset(e, sx.clock, sx.reset, sx.init)
initialize(e)
sx
- case sx @ IsInvalid(info, expr) =>
- val wref = netlist(expr) match { case e: WRef => e }
- declare("reg", wref.name, sx.expr.tpe, info)
- initialize(wref)
- kind(expr) match {
- case PortKind | WireKind | InstanceKind => assign(expr, netlist(expr), info)
- case _ =>
- }
- sx
case sx: DefNode =>
declare("wire", sx.name, sx.value.tpe, sx.info)
assign(WRef(sx.name, sx.value.tpe, NodeKind, MALE), sx.value, sx.info)
@@ -694,6 +683,18 @@ class VerilogEmitter extends SeqTransform with Emitter {
emit(Seq("`endif"))
}
if (initials.nonEmpty) {
+ emit(Seq("`ifdef RANDOMIZE_GARBAGE_ASSIGN"))
+ emit(Seq("`define RANDOMIZE"))
+ emit(Seq("`endif"))
+ emit(Seq("`ifdef RANDOMIZE_INVALID_ASSIGN"))
+ emit(Seq("`define RANDOMIZE"))
+ emit(Seq("`endif"))
+ emit(Seq("`ifdef RANDOMIZE_REG_INIT"))
+ emit(Seq("`define RANDOMIZE"))
+ emit(Seq("`endif"))
+ emit(Seq("`ifdef RANDOMIZE_MEM_INIT"))
+ emit(Seq("`define RANDOMIZE"))
+ emit(Seq("`endif"))
emit(Seq("`ifdef RANDOMIZE"))
emit(Seq(" integer initvar;"))
emit(Seq(" initial begin"))
@@ -706,6 +707,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
for (x <- initials) emit(Seq(tab, x))
emit(Seq(" end"))
emit(Seq("`endif // RANDOMIZE"))
+ emit(Seq("`undef RANDOMIZE"))
}
for (clk_stream <- at_clock if clk_stream._2.nonEmpty) {
@@ -724,22 +726,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
}
/** Preamble for every emitted Verilog file */
- def preamble: String =
- """|`ifdef RANDOMIZE_GARBAGE_ASSIGN
- |`define RANDOMIZE
- |`endif
- |`ifdef RANDOMIZE_INVALID_ASSIGN
- |`define RANDOMIZE
- |`endif
- |`ifdef RANDOMIZE_REG_INIT
- |`define RANDOMIZE
- |`endif
- |`ifdef RANDOMIZE_MEM_INIT
- |`define RANDOMIZE
- |`endif
- |
- |""".stripMargin
-
def transforms = Seq(
passes.VerilogModulusCleanup,
passes.VerilogWrap,
@@ -747,8 +733,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
passes.VerilogPrep)
def emit(state: CircuitState, writer: Writer): Unit = {
- writer.write(preamble)
-
val circuit = runTransforms(state).circuit
val moduleMap = circuit.modules.map(m => m.name -> m).toMap
circuit.modules.foreach {
@@ -771,7 +755,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
circuit.modules flatMap {
case module: Module =>
val writer = new java.io.StringWriter
- writer.write(preamble)
emit_verilog(module, moduleMap)(writer)
Some(EmittedVerilogModuleAnnotation(EmittedVerilogModule(module.name, writer.toString)))
case _: ExtModule => None
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 06f0874a..68d16c30 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -30,7 +30,7 @@ object RemoveValidIf extends Pass {
// Recursive. Replaces IsInvalid with connecting zero
private def onStmt(s: Statement): Statement = s map onStmt map onExp match {
case invalid @ IsInvalid(info, loc) => loc.tpe match {
- case _: AnalogType => invalid // Unclear what we should do, can't remove or we emit invalid Firrtl
+ case _: AnalogType => EmptyStmt
case tpe => Connect(info, loc, getGroundZero(tpe))
}
// Register connected to itself (since reset has been made explicit) is a register with no reset
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index 6e5883d7..cf92ec1c 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -233,6 +233,36 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
|endmodule""".stripMargin.split("\n") map normalized
executeTest(input, check, compiler)
}
+
+ it should "not error if not isinvalid" in {
+ val compiler = new VerilogCompiler
+ val input =
+ """circuit Attaching :
+ | module Attaching :
+ | output an: Analog<3>
+ |""".stripMargin
+ val check =
+ """module Attaching(
+ | inout [2:0] an
+ |);
+ |endmodule""".stripMargin.split("\n") map normalized
+ executeTest(input, check, compiler)
+ }
+ it should "not error if isinvalid" in {
+ val compiler = new VerilogCompiler
+ val input =
+ """circuit Attaching :
+ | module Attaching :
+ | output an: Analog<3>
+ | an is invalid
+ |""".stripMargin
+ val check =
+ """module Attaching(
+ | inout [2:0] an
+ |);
+ |endmodule""".stripMargin.split("\n") map normalized
+ executeTest(input, check, compiler)
+ }
}
class AttachAnalogSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 39d54755..348ed300 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -133,40 +133,23 @@ circuit Top :
* to the correct Verilog.
*/
class VerilogCompilerSpec extends CompilerSpec with Matchers {
- val compiler = new VerilogCompiler()
- val input =
-"""
-circuit Top :
- module Top :
- input a : UInt<1>[2]
- output b : UInt<1>[2]
- b <= a
-"""
- val check = Seq(
- "`ifdef RANDOMIZE_GARBAGE_ASSIGN",
- "`define RANDOMIZE",
- "`endif",
- "`ifdef RANDOMIZE_INVALID_ASSIGN",
- "`define RANDOMIZE",
- "`endif",
- "`ifdef RANDOMIZE_REG_INIT",
- "`define RANDOMIZE",
- "`endif",
- "`ifdef RANDOMIZE_MEM_INIT",
- "`define RANDOMIZE",
- "`endif",
- "",
- "module Top(",
- " input a_0,",
- " input a_1,",
- " output b_0,",
- " output b_1",
- ");",
- " assign b_0 = a_0;",
- " assign b_1 = a_1;",
- "endmodule\n"
- ).reduce(_ + "\n" + _)
- "A circuit's verilog output" should "match the given string" in {
+ val input = """circuit Top :
+ | module Top :
+ | input a : UInt<1>[2]
+ | output b : UInt<1>[2]
+ | b <= a""".stripMargin
+ val check = """module Top(
+ | input a_0,
+ | input a_1,
+ | output b_0,
+ | output b_1
+ |);
+ | assign b_0 = a_0;
+ | assign b_1 = a_1;
+ |endmodule
+ |""".stripMargin
+ def compiler = new VerilogCompiler()
+ "A circuit's verilog output" should "match the given string and not have RANDOMIZE if no invalids" in {
getOutput should be (check)
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 19:31:44 +0000