1 files changed, 21 insertions, 11 deletions
diff --git a/src/main/scala/firrtl/analyses/Netlist.scala b/src/main/scala/firrtl/analyses/Netlist.scala
index c83dcc2b..f00e96bb 100644
--- a/src/main/scala/firrtl/analyses/Netlist.scala
+++ b/src/main/scala/firrtl/analyses/Netlist.scala
@@ -25,26 +25,36 @@ class InstanceGraph(c: Circuit) {
   }
 
   private val moduleMap = c.modules.map({m => (m.name,m) }).toMap
+  private val instantiated = new mutable.HashSet[String]
   private val childInstances =
     new mutable.HashMap[String,mutable.Set[WDefInstance]]
   for (m <- c.modules) {
     childInstances(m.name) = new mutable.HashSet[WDefInstance]
     m map collectInstances(childInstances(m.name))
+    instantiated ++= childInstances(m.name).map(i => i.module)
   }
+
+  private val uninstantiated = moduleMap.keySet -- instantiated
   private val instanceGraph = new MutableDiGraph[WDefInstance]
   private val instanceQueue = new mutable.Queue[WDefInstance]
-  private val topInstance = WDefInstance(c.main,c.main) // top instance
-  instanceQueue.enqueue(topInstance)
-  while (!instanceQueue.isEmpty) {
-    val current = instanceQueue.dequeue
-    instanceGraph.addVertex(current)
-    for (child <- childInstances(current.module)) {
-      if (!instanceGraph.contains(child)) {
-        instanceQueue.enqueue(child)
+
+  uninstantiated.foreach({ subTop =>
+    val topInstance = WDefInstance(subTop,subTop)
+    instanceQueue.enqueue(topInstance)
+    while (!instanceQueue.isEmpty) {
+      val current = instanceQueue.dequeue
+      instanceGraph.addVertex(current)
+      for (child <- childInstances(current.module)) {
+        if (!instanceGraph.contains(child)) {
+          instanceQueue.enqueue(child)
+        }
+        instanceGraph.addEdge(current,child)
       }
-      instanceGraph.addEdge(current,child)
     }
-  }
+  })
+
+  // The true top module (circuit main)
+  private val trueTopInstance = WDefInstance(c.main, c.main)
 
   /** A directed graph showing the instance dependencies among modules
     * in the circuit. Every WDefInstance of a module has an edge to
@@ -56,7 +66,7 @@ class InstanceGraph(c: Circuit) {
   /** A list of absolute paths (each represented by a Seq of instances)
     * of all module instances in the Circuit.
     */
-  lazy val fullHierarchy = graph.pathsInDAG(topInstance)
+  lazy val fullHierarchy = graph.pathsInDAG(trueTopInstance)
 
   /** Finds the absolute paths (each represented by a Seq of instances
     * representing the chain of hierarchy) of all instances of a