diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogRename.scala | 11 |
2 files changed, 1 insertions, 12 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index d29ab367..14d222f6 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -6,7 +6,7 @@ import firrtl.transforms.IdentityTransform import firrtl.options.StageUtils import firrtl.stage.{Forms, TransformManager} -@deprecated("Use a TransformManager or some other Stage/Phase class. Will be removed in 1.3.", "1.2") +@deprecated("Use a TransformManager or some other Stage/Phase class. Will be removed in 1.4.", "FIRRTL 1.2") sealed abstract class CoreTransform extends SeqTransform /** This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting diff --git a/src/main/scala/firrtl/passes/VerilogRename.scala b/src/main/scala/firrtl/passes/VerilogRename.scala deleted file mode 100644 index 4d51128c..00000000 --- a/src/main/scala/firrtl/passes/VerilogRename.scala +++ /dev/null @@ -1,11 +0,0 @@ -package firrtl.passes -import firrtl.ir.Circuit -import firrtl.transforms.VerilogRename - -@deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2") -object VerilogRename extends Pass { - override def run(c: Circuit): Circuit = new VerilogRename().run(c) - @deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2") - def verilogRenameN(n: String): String = - if (firrtl.Utils.v_keywords(n)) "%s$".format(n) else n -} |