diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/flo.stanza | 9 | ||||
| -rw-r--r-- | src/main/stanza/ir-utils.stanza | 13 | ||||
| -rw-r--r-- | src/main/stanza/verilog.stanza | 16 |
3 files changed, 19 insertions, 19 deletions
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index bb9365ae..22b0c978 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -60,11 +60,14 @@ defn pad-widths-e (desired:Int,e:Expression) -> Expression : if i > desired : trim(desired, e) else : SIntValue(value(e),IntWidth(desired)) (e:Register) : - trim-pad(desired, Register(type(e), pad-widths-e(int-width!(type(e)), value(e)), pad-widths-e(1, enable(e)))) + val value* = pad-widths-e(desired, value(e)) + Register(type(value*), value*, pad-widths-e(1, enable(e))) (e:ReadPort) : - trim-pad(desired, ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))) + if int-width!(type(e)) != desired : error("ReadPort has different width than desired") + else : ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))) (e:WritePort) : - trim-pad(desired, WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))) + if int-width!(type(e)) != desired : error("WritePort has different width than desired") + else : WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))) (e) : error(to-string $ e) defn pad-widths-s (s:Stmt) -> Stmt : diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 1d209622..8b198c64 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -445,11 +445,12 @@ public defn merge!<?K,?V> (a:HashTable<?K,?V>, b:HashTable<K,V>) : a[key(e)] = value(e) public defn pow (x:Int,y:Int) -> Int : - var x* = 1 - var y* = y - while y* != 0 : - x* = x* * x - y* = y* - 1 - x* + var x* = to-long(1) + var y* = to-long(y) + while y* != to-long(0) : + x* = x* * to-long(x) + y* = y* - to-long(1) + if x* > to-long(2147483647) : error("Value too big for Int") + else : to-int $ to-string(x*) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 50ea1fc1..96778469 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -80,7 +80,8 @@ defn emit (e:Expression) -> String : val x = args(e)[0] val w = width!(type(x)) val diff = consts(e)[0] - w - ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"] + if w == 0 : [ emit(x) ] + else : ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"] AS-UINT-OP : ["$unsigned(" emit(args(e)[0]) ")"] AS-SINT-OP : @@ -100,7 +101,7 @@ defn emit (e:Expression) -> String : BIT-XOR-OP : [emit(args(e)[0]) " ^ " emit(args(e)[1])] CONCAT-OP : ["{" emit(args(e)[0]) "," emit(args(e)[1]) "}"] BIT-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] "]"] - BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[1] ":" consts(e)[0] "]"] + BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] ":" consts(e)[1] "]"] BIT-AND-REDUCE-OP : var v = emit(args(e)[0]) for x in tail(args(e)) do : @@ -161,14 +162,9 @@ defn emit-module (m:InModule) : add(inst-ports[name(s)], ["." name(f) "( " n* " )"]) (s:DefMemory) : val vtype = type(s) as VectorType - if seq?(s) : - add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) - add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"]) - else : - add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) - add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"]) + add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) + add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) + add(inits,[" " name(s) "[initvar] = {" width!(type(vtype)) "{$random}};"]) (s:DefNode) : add(wires,["wire " get-width(type(value(s))) " " name(s) ";"]) add(assigns,["assign " name(s) " = " emit(value(s)) ";"]) |