aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Emitter.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index eb219b6d..9e78cbb3 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -102,7 +102,7 @@ class VerilogEmitter extends Emitter with PassBased {
case (s: Seq[Any]) =>
s foreach (emit(_, top + 1))
if (top == 0) w write "\n"
- case _ => error("Shouldn't be here")
+ case x => println(x); throwInternalError;
}
}