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-rw-r--r--src/main/stanza/compilers.stanza7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 0c3978ab..67c6bfeb 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -41,13 +41,8 @@ public defstruct StandardVerilog <: Compiler :
file: String with: (as-method => true)
public defmethod passes (c:StandardVerilog) -> List<Pass> :
to-list $ [
-<<<<<<< HEAD
- CheckHighForm()
- ;; TempElimination()
-=======
CheckHighForm(expand-delin)
- TempElimination()
->>>>>>> upstream/master
+ ;; TempElimination()
ToWorkingIR()
MakeExplicitReset()
ResolveKinds()