2 files changed, 26 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 8717ffec..3c9a7eda 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -35,6 +35,8 @@ trait CheckHighFormLike { this: Pass =>
     s"$info: [module $mname] Invalid access to non-reference.")
   class ModuleNameNotUniqueException(info: Info, mname: String) extends PassException(
     s"$info: Repeat definition of module $mname")
+  class DefnameConflictException(info: Info, mname: String, defname: String) extends PassException(
+    s"$info: defname $defname of extmodule $mname conflicts with an existing module")
   class ModuleNotDefinedException(info: Info, mname: String, name: String) extends PassException(
     s"$info: Module $name is not defined.")
   class IncorrectNumArgsException(info: Info, mname: String, op: String, n: Int) extends PassException(
@@ -75,10 +77,17 @@ trait CheckHighFormLike { this: Pass =>
     val moduleGraph = new ModuleGraph
     val moduleNames = (c.modules map (_.name)).toSet
 
+    val intModuleNames = c.modules.view.collect({ case m: Module => m.name }).toSet
+
     c.modules.view.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach {
       m => errors.append(new ModuleNameNotUniqueException(m.info, m.name))
     }
 
+    c.modules.collect {
+      case ExtModule(info, name, _, defname, _) if (intModuleNames.contains(defname)) =>
+        errors.append(new DefnameConflictException(info, name, defname))
+    }
+
     def checkHighFormPrimop(info: Info, mname: String, e: DoPrim): Unit = {
       def correctNum(ne: Option[Int], nc: Int): Unit = {
         ne match {
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index f03b6611..aa154bab 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -333,6 +333,23 @@ class CheckSpec extends FlatSpec with Matchers {
     }
   }
 
+  s"Defnames that conflict with pure-FIRRTL module names" should "throw an exception" in {
+    val input =
+      s"""|circuit bar :
+          |  module bar :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    o <= i
+          |  extmodule dup :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    defname = bar
+          |""".stripMargin
+    assertThrows[CheckHighForm.DefnameConflictException] {
+      checkHighInput(input)
+    }
+  }
+
 }
 
 object CheckSpec {