2 files changed, 44 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 0df052af..66ae1673 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -85,6 +85,7 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform {
     passes.ResolveGenders,
     passes.InferWidths,
     passes.Legalize,
+    new firrtl.transforms.RemoveReset,
     new firrtl.transforms.CheckCombLoops)
 }
 
diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala
new file mode 100644
index 00000000..bfec76a2
--- /dev/null
+++ b/src/main/scala/firrtl/transforms/RemoveReset.scala
@@ -0,0 +1,43 @@
+// See LICENSE for license details.
+
+package firrtl
+package transforms
+
+import firrtl.ir._
+import firrtl.Mappers._
+
+import scala.collection.mutable
+
+/** Remove Synchronous Reset
+  *
+  * @note This pass must run after LowerTypes
+  */
+class RemoveReset extends Transform {
+  def inputForm = MidForm
+  def outputForm = MidForm
+
+  private case class Reset(cond: Expression, value: Expression)
+
+  private def onModule(m: DefModule): DefModule = {
+    val resets = mutable.HashMap.empty[String, Reset]
+    def onStmt(stmt: Statement): Statement = {
+      stmt match {
+        case reg @ DefRegister(_, rname, _, _, reset, init) if reset != Utils.zero =>
+          // Add register reset to map
+          resets(rname) = Reset(reset, init)
+          reg.copy(reset = Utils.zero, init = WRef(reg))
+        case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if resets.contains(rname) =>
+          val reset = resets(rname)
+          val muxType = Utils.mux_type_and_widths(reset.value, expr)
+          Connect(info, ref, Mux(reset.cond, reset.value, expr, muxType))
+        case other => other map onStmt
+      }
+    }
+    m.map(onStmt)
+  }
+
+  def execute(state: CircuitState): CircuitState = {
+    val c = state.circuit.map(onModule)
+    state.copy(circuit = c)
+  }
+}