3 files changed, 5 insertions, 5 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index b9a3028a..1e978a2e 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -49,11 +49,11 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       TempElimination()        ;R
       ToWorkingIR()            ;R -> W
       ResolveKinds()           ;W
-      CheckKinds()             ;W
       InferTypes()             ;R
-      CheckTypes()             ;R
       ResolveGenders()         ;W
       CheckGenders()           ;W
+      CheckKinds()             ;W
+      CheckTypes()             ;R
       ExpandAccessors()        ;W
       LowerToGround()          ;W
       ExpandIndexedConnects()  ;W
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 69073f9f..4bcf8dd7 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -653,7 +653,8 @@ public defn check-types (c:Circuit) -> Circuit :
             (s:Connect) : 
                if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
             (s:BulkConnect) : 
-               if not bulk-equals?(type(loc(s)),type(exp(s))) : add(errors,InvalidConnect(info(s)))
+               if not bulk-equals?(type(loc(s)),type(exp(s))) : 
+                  add(errors,InvalidConnect(info(s)))
             (s:OnReset) : 
                if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
                if has-flip?(type(loc(s))) : add(errors,OnResetIllegalFlips(info(s)))
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index fead9ac2..99fb8172 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -217,7 +217,7 @@ defn hasWidth (e:?) :
 defn hasType (e:?) :
    e typeof Ref|Subfield|Index|DoPrim|WRef|WSubfield
       |WIndex|DefWire|DefRegister|DefMemory|DefPoison
-      |VectorType|Port|Field|UIntValue|SIntValue
+      |VectorType|Port|UIntValue|SIntValue
 
 defn hasKind (e:?) :
    e typeof WRef
@@ -600,7 +600,6 @@ defn resolve-kinds (c:Circuit) :
       kinds[name(m)] = ModuleKind()
       for p in ports(m) do :
          kinds[name(p)] = PortKind()
-      println(name(m))
       match(m) : 
          (m:InModule) : find-stmt(body(m))
          (m:ExModule) : false