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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 46e1716c..a4f5c14d 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -657,7 +657,7 @@ class VerilogEmitter extends Emitter { // then start the simulation later // Verilator does not support delay statements, so they are omitted. emit(Seq(" `ifndef verilator")) - emit(Seq(" #0.002;")) + emit(Seq(" #0.002 begin end")) emit(Seq(" `endif")) for (x <- initials) { emit(Seq(tab,x)) |