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-rw-r--r--src/main/scala/firrtl/Emitter.scala11
-rw-r--r--src/main/scala/firrtl/IR.scala18
-rw-r--r--src/main/scala/firrtl/Mappers.scala10
-rw-r--r--src/main/scala/firrtl/Serialize.scala12
-rw-r--r--src/main/scala/firrtl/Utils.scala18
-rw-r--r--src/main/scala/firrtl/Visitor.scala10
-rw-r--r--src/main/scala/firrtl/WIR.scala4
-rw-r--r--src/main/scala/firrtl/passes/Checks.scala18
-rw-r--r--src/main/scala/firrtl/passes/ConstProp.scala54
-rw-r--r--src/main/scala/firrtl/passes/LowerTypes.scala2
-rw-r--r--src/main/scala/firrtl/passes/Passes.scala60
-rw-r--r--src/main/scala/firrtl/passes/Uniquify.scala4
12 files changed, 112 insertions, 109 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index c8657131..1b171d3a 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -89,9 +89,8 @@ class VerilogEmitter extends Emitter {
case (e:WSubField) => w.get.write(LowerTypes.loweredName(e))
case (e:WSubAccess) => w.get.write(LowerTypes.loweredName(e.exp) + "[" + LowerTypes.loweredName(e.index) + "]")
case (e:WSubIndex) => w.get.write(e.serialize)
- case (_:UIntValue|_:SIntValue) => v_print(e)
+ case (e:Literal) => v_print(e)
case VRandom => w.get.write("$random")
-
}
}
case (t:Type) => {
@@ -126,11 +125,11 @@ class VerilogEmitter extends Emitter {
//;------------- PASS -----------------
def v_print (e:Expression) = {
e match {
- case (e:UIntValue) => {
+ case (e:UIntLiteral) => {
val str = e.value.toString(16)
w.get.write(long_BANG(tpe(e)).toString + "'h" + str)
}
- case (e:SIntValue) => {
+ case (e:SIntLiteral) => {
val str = e.value.toString(16)
w.get.write(long_BANG(tpe(e)).toString + "'sh" + str)
}
@@ -164,8 +163,8 @@ class VerilogEmitter extends Emitter {
def c1 () : Int = doprim.consts(1).toInt
def checkArgumentLegality(e: Expression) = e match {
- case _: UIntValue =>
- case _: SIntValue =>
+ case _: UIntLiteral =>
+ case _: SIntLiteral =>
case _: WRef =>
case _: WSubField =>
case _ => throw new EmitterException(s"Can't emit ${e.getClass.getName} as PrimOp argument")
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 8bd8192b..840fef03 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -92,19 +92,23 @@ case object BITS_SELECT_OP extends PrimOp
case object HEAD_OP extends PrimOp
case object TAIL_OP extends PrimOp
-trait Expression extends AST {
+abstract class Expression extends AST {
def tpe: Type
}
-case class Ref(name: String, tpe: Type) extends Expression with HasName
-case class SubField(exp: Expression, name: String, tpe: Type) extends Expression with HasName
-case class SubIndex(exp: Expression, value: Int, tpe: Type) extends Expression
-case class SubAccess(exp: Expression, index: Expression, tpe: Type) extends Expression
+case class Reference(name: String, tpe: Type) extends Expression with HasName
+case class SubField(expr: Expression, name: String, tpe: Type) extends Expression with HasName
+case class SubIndex(expr: Expression, value: Int, tpe: Type) extends Expression
+case class SubAccess(expr: Expression, index: Expression, tpe: Type) extends Expression
case class Mux(cond: Expression, tval: Expression, fval: Expression, tpe: Type) extends Expression
case class ValidIf(cond: Expression, value: Expression, tpe: Type) extends Expression
-case class UIntValue(value: BigInt, width: Width) extends Expression {
+abstract class Literal extends Expression {
+ val value: BigInt
+ val width: Width
+}
+case class UIntLiteral(value: BigInt, width: Width) extends Literal {
def tpe = UIntType(width)
}
-case class SIntValue(value: BigInt, width: Width) extends Expression {
+case class SIntLiteral(value: BigInt, width: Width) extends Literal {
def tpe = SIntType(width)
}
case class DoPrim(op: PrimOp, args: Seq[Expression], consts: Seq[BigInt], tpe: Type) extends Expression
diff --git a/src/main/scala/firrtl/Mappers.scala b/src/main/scala/firrtl/Mappers.scala
index aeb67f3d..dc8c6d37 100644
--- a/src/main/scala/firrtl/Mappers.scala
+++ b/src/main/scala/firrtl/Mappers.scala
@@ -101,9 +101,9 @@ object Mappers {
implicit def forExp(f: Expression => Expression) = new ExpMagnet {
override def map(exp: Expression): Expression = {
exp match {
- case e: SubField => SubField(f(e.exp), e.name, e.tpe)
- case e: SubIndex => SubIndex(f(e.exp), e.value, e.tpe)
- case e: SubAccess => SubAccess(f(e.exp), f(e.index), e.tpe)
+ case e: SubField => SubField(f(e.expr), e.name, e.tpe)
+ case e: SubIndex => SubIndex(f(e.expr), e.value, e.tpe)
+ case e: SubAccess => SubAccess(f(e.expr), f(e.index), e.tpe)
case e: Mux => Mux(f(e.cond), f(e.tval), f(e.fval), e.tpe)
case e: ValidIf => ValidIf(f(e.cond), f(e.value), e.tpe)
case e: DoPrim => DoPrim(e.op, e.args.map(f), e.consts, e.tpe)
@@ -131,8 +131,8 @@ object Mappers {
implicit def forWidth(f: Width => Width) = new ExpMagnet {
override def map(exp: Expression): Expression = {
exp match {
- case e: UIntValue => UIntValue(e.value,f(e.width))
- case e: SIntValue => SIntValue(e.value,f(e.width))
+ case e: UIntLiteral => UIntLiteral(e.value,f(e.width))
+ case e: SIntLiteral => SIntLiteral(e.value,f(e.width))
case e => e
}
}
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index cec1271f..e5bf166c 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -66,12 +66,12 @@ class Serialize {
def serialize(exp: Expression): String = {
exp match {
- case v: UIntValue => s"UInt${serialize(v.width)}(${serialize(v.value)})"
- case v: SIntValue => s"SInt${serialize(v.width)}(${serialize(v.value)})"
- case r: Ref => r.name
- case s: SubField => s"${serialize(s.exp)}.${s.name}"
- case s: SubIndex => s"${serialize(s.exp)}[${s.value}]"
- case s: SubAccess => s"${serialize(s.exp)}[${serialize(s.index)}]"
+ case v: UIntLiteral => s"UInt${serialize(v.width)}(${serialize(v.value)})"
+ case v: SIntLiteral => s"SInt${serialize(v.width)}(${serialize(v.value)})"
+ case r: Reference => r.name
+ case s: SubField => s"${serialize(s.expr)}.${s.name}"
+ case s: SubIndex => s"${serialize(s.expr)}[${s.value}]"
+ case s: SubAccess => s"${serialize(s.expr)}[${serialize(s.index)}]"
case m: Mux => s"mux(${serialize(m.cond)}, ${serialize(m.tval)}, ${serialize(m.fval)})"
case v: ValidIf => s"validif(${serialize(v.cond)}, ${serialize(v.value)})"
case p: DoPrim =>
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 1308f2c3..9f85949c 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -73,12 +73,12 @@ object Utils extends LazyLogging {
val gen_names = Map[String,Int]()
val delin = "_"
def BoolType () = { UIntType(IntWidth(1)) }
- val one = UIntValue(BigInt(1),IntWidth(1))
- val zero = UIntValue(BigInt(0),IntWidth(1))
- def uint (i:Int) : UIntValue = {
+ val one = UIntLiteral(BigInt(1),IntWidth(1))
+ val zero = UIntLiteral(BigInt(0),IntWidth(1))
+ def uint (i:Int) : UIntLiteral = {
val num_bits = req_num_bits(i)
val w = IntWidth(scala.math.max(1,num_bits - 1))
- UIntValue(BigInt(i),w)
+ UIntLiteral(BigInt(i),w)
}
def req_num_bits (i: Int) : Int = {
val ix = if (i < 0) ((-1 * i) - 1) else i
@@ -465,8 +465,8 @@ object Utils extends LazyLogging {
case e:WSubIndex => e.gender
case e:WSubAccess => e.gender
case e:DoPrim => MALE
- case e:UIntValue => MALE
- case e:SIntValue => MALE
+ case e:UIntLiteral => MALE
+ case e:SIntLiteral => MALE
case e:Mux => MALE
case e:ValidIf => MALE
case e:WInvalid => MALE
@@ -499,7 +499,7 @@ object Utils extends LazyLogging {
}
def tpe (e:Expression) : Type =
e match {
- case e:Ref => e.tpe
+ case e:Reference => e.tpe
case e:SubField => e.tpe
case e:SubIndex => e.tpe
case e:SubAccess => e.tpe
@@ -510,8 +510,8 @@ object Utils extends LazyLogging {
case e:DoPrim => e.tpe
case e:Mux => e.tpe
case e:ValidIf => e.tpe
- case e:UIntValue => UIntType(e.width)
- case e:SIntValue => SIntType(e.width)
+ case e:UIntLiteral => UIntType(e.width)
+ case e:SIntLiteral => SIntType(e.width)
case e:WVoid => UnknownType
case e:WInvalid => UnknownType
}
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index cc4d9c74..db2e8b8b 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -200,8 +200,8 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
case "reg" => {
val name = (ctx.id(0).getText)
val tpe = visitType(ctx.`type`(0))
- val reset = if (ctx.exp(1) != null) visitExp(ctx.exp(1)) else UIntValue(0, IntWidth(1))
- val init = if (ctx.exp(2) != null) visitExp(ctx.exp(2)) else Ref(name, tpe)
+ val reset = if (ctx.exp(1) != null) visitExp(ctx.exp(1)) else UIntLiteral(0, IntWidth(1))
+ val init = if (ctx.exp(2) != null) visitExp(ctx.exp(2)) else Reference(name, tpe)
DefRegister(info, name, tpe, visitExp(ctx.exp(0)), reset, init)
}
case "mem" => visitMem(ctx)
@@ -251,7 +251,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
// - Add validif
private def visitExp[AST](ctx: FIRRTLParser.ExpContext): Expression =
if( ctx.getChildCount == 1 )
- Ref((ctx.getText), UnknownType)
+ Reference((ctx.getText), UnknownType)
else
ctx.getChild(0).getText match {
case "UInt" => { // This could be better
@@ -262,7 +262,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
val bigint = string2BigInt(ctx.IntLit(0).getText)
(IntWidth(BigInt(scala.math.max(bigint.bitLength,1))),bigint)
}
- UIntValue(value, width)
+ UIntLiteral(value, width)
}
case "SInt" => {
val (width, value) =
@@ -272,7 +272,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
val bigint = string2BigInt(ctx.IntLit(0).getText)
(IntWidth(BigInt(bigint.bitLength + 1)),bigint)
}
- SIntValue(value, width)
+ SIntLiteral(value, width)
}
case "validif(" => ValidIf(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType)
case "mux(" => Mux(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), visitExp(ctx.exp(2)), UnknownType)
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index cdd00e07..3bff3e1e 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -79,8 +79,8 @@ class WrappedExpression (val e1:Expression) {
we match {
case (we:WrappedExpression) => {
(e1,we.e1) match {
- case (e1:UIntValue,e2:UIntValue) => if (e1.value == e2.value) eqw(e1.width,e2.width) else false
- case (e1:SIntValue,e2:SIntValue) => if (e1.value == e2.value) eqw(e1.width,e2.width) else false
+ case (e1:UIntLiteral,e2:UIntLiteral) => if (e1.value == e2.value) eqw(e1.width,e2.width) else false
+ case (e1:SIntLiteral,e2:SIntLiteral) => if (e1.value == e2.value) eqw(e1.width,e2.width) else false
case (e1:WRef,e2:WRef) => e1.name equals e2.name
case (e1:WSubField,e2:WSubField) => (e1.name equals e2.name) && weq(e1.exp,e2.exp)
case (e1:WSubIndex,e2:WSubIndex) => (e1.value == e2.value) && weq(e1.exp,e2.exp)
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 272c96ea..1a11c0a4 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -148,7 +148,7 @@ object CheckHighForm extends Pass with LazyLogging {
}
def checkValidLoc(e: Expression) = {
e match {
- case e @ ( _: UIntValue | _: SIntValue | _: DoPrim ) => errors.append(new InvalidLOCException)
+ case e @ (_: UIntLiteral | _: SIntLiteral | _: DoPrim ) => errors.append(new InvalidLOCException)
case _ => // Do Nothing
}
}
@@ -189,7 +189,7 @@ object CheckHighForm extends Pass with LazyLogging {
validSubexp(e.exp)
e
}
- case e: UIntValue =>
+ case e: UIntLiteral =>
if (e.value < 0) errors.append(new NegUIntException)
case e => e map (validSubexp)
}
@@ -411,7 +411,7 @@ object CheckTypes extends Pass with LazyLogging {
if (!passive(tpe(e))) errors.append(new ValidIfPassiveTypes(info))
if (!(tpe(e.cond).typeof[UIntType])) errors.append(new ValidIfCondUInt(info))
}
- case (_:UIntValue|_:SIntValue) => false
+ case (_:UIntLiteral | _:SIntLiteral) => false
}
e
}
@@ -560,8 +560,8 @@ object CheckGenders extends Pass {
case (e:WSubIndex) => get_gender(e.exp,genders)
case (e:WSubAccess) => get_gender(e.exp,genders)
case (e:DoPrim) => MALE
- case (e:UIntValue) => MALE
- case (e:SIntValue) => MALE
+ case (e:UIntLiteral) => MALE
+ case (e:SIntLiteral) => MALE
case (e:Mux) => MALE
case (e:ValidIf) => MALE
}
@@ -577,8 +577,8 @@ object CheckGenders extends Pass {
case (e:DoPrim) => for (e <- e.args ) { check_gender(info,genders,MALE)(e) }
case (e:Mux) => e map (check_gender(info,genders,MALE))
case (e:ValidIf) => e map (check_gender(info,genders,MALE))
- case (e:UIntValue) => false
- case (e:SIntValue) => false
+ case (e:UIntLiteral) => false
+ case (e:SIntLiteral) => false
}
e
}
@@ -659,7 +659,7 @@ object CheckWidths extends Pass {
}
def check_width_e (info:Info)(e:Expression) : Expression = {
(e map (check_width_e(info))) match {
- case (e:UIntValue) => {
+ case (e:UIntLiteral) => {
(e.width) match {
case (w:IntWidth) =>
if (scala.math.max(1,e.value.bitLength) > w.width) {
@@ -669,7 +669,7 @@ object CheckWidths extends Pass {
}
check_width_w(info)(e.width)
}
- case (e:SIntValue) => {
+ case (e:SIntLiteral) => {
(e.width) match {
case (w:IntWidth) =>
if (e.value.bitLength + 1 > w.width) errors.append(new WidthTooSmall(info, e.value))
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index 11c14e56..e562f71d 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -37,20 +37,20 @@ object ConstProp extends Pass {
def name = "Constant Propagation"
trait FoldLogicalOp {
- def fold(c1: UIntValue, c2: UIntValue): UIntValue
- def simplify(e: Expression, lhs: UIntValue, rhs: Expression): Expression
+ def fold(c1: UIntLiteral, c2: UIntLiteral): UIntLiteral
+ def simplify(e: Expression, lhs: UIntLiteral, rhs: Expression): Expression
def apply(e: DoPrim): Expression = (e.args(0), e.args(1)) match {
- case (lhs: UIntValue, rhs: UIntValue) => fold(lhs, rhs)
- case (lhs: UIntValue, rhs) => simplify(e, lhs, rhs)
- case (lhs, rhs: UIntValue) => simplify(e, rhs, lhs)
+ case (lhs: UIntLiteral, rhs: UIntLiteral) => fold(lhs, rhs)
+ case (lhs: UIntLiteral, rhs) => simplify(e, lhs, rhs)
+ case (lhs, rhs: UIntLiteral) => simplify(e, rhs, lhs)
case _ => e
}
}
object FoldAND extends FoldLogicalOp {
- def fold(c1: UIntValue, c2: UIntValue) = UIntValue(c1.value & c2.value, c1.width max c2.width)
- def simplify(e: Expression, lhs: UIntValue, rhs: Expression) = lhs.width match {
+ def fold(c1: UIntLiteral, c2: UIntLiteral) = UIntLiteral(c1.value & c2.value, c1.width max c2.width)
+ def simplify(e: Expression, lhs: UIntLiteral, rhs: Expression) = lhs.width match {
case IntWidth(w) if long_BANG(tpe(rhs)) == w =>
if (lhs.value == 0) lhs // and(x, 0) => 0
else if (lhs.value == (BigInt(1) << w.toInt) - 1) rhs // and(x, 1) => x
@@ -60,8 +60,8 @@ object ConstProp extends Pass {
}
object FoldOR extends FoldLogicalOp {
- def fold(c1: UIntValue, c2: UIntValue) = UIntValue(c1.value | c2.value, c1.width max c2.width)
- def simplify(e: Expression, lhs: UIntValue, rhs: Expression) = lhs.width match {
+ def fold(c1: UIntLiteral, c2: UIntLiteral) = UIntLiteral(c1.value | c2.value, c1.width max c2.width)
+ def simplify(e: Expression, lhs: UIntLiteral, rhs: Expression) = lhs.width match {
case IntWidth(w) if long_BANG(tpe(rhs)) == w =>
if (lhs.value == 0) rhs // or(x, 0) => x
else if (lhs.value == (BigInt(1) << w.toInt) - 1) lhs // or(x, 1) => 1
@@ -71,8 +71,8 @@ object ConstProp extends Pass {
}
object FoldXOR extends FoldLogicalOp {
- def fold(c1: UIntValue, c2: UIntValue) = UIntValue(c1.value ^ c2.value, c1.width max c2.width)
- def simplify(e: Expression, lhs: UIntValue, rhs: Expression) = lhs.width match {
+ def fold(c1: UIntLiteral, c2: UIntLiteral) = UIntLiteral(c1.value ^ c2.value, c1.width max c2.width)
+ def simplify(e: Expression, lhs: UIntLiteral, rhs: Expression) = lhs.width match {
case IntWidth(w) if long_BANG(tpe(rhs)) == w =>
if (lhs.value == 0) rhs // xor(x, 0) => x
else e
@@ -81,8 +81,8 @@ object ConstProp extends Pass {
}
object FoldEqual extends FoldLogicalOp {
- def fold(c1: UIntValue, c2: UIntValue) = UIntValue(if (c1.value == c2.value) 1 else 0, IntWidth(1))
- def simplify(e: Expression, lhs: UIntValue, rhs: Expression) = lhs.width match {
+ def fold(c1: UIntLiteral, c2: UIntLiteral) = UIntLiteral(if (c1.value == c2.value) 1 else 0, IntWidth(1))
+ def simplify(e: Expression, lhs: UIntLiteral, rhs: Expression) = lhs.width match {
case IntWidth(w) if w == 1 && long_BANG(tpe(rhs)) == 1 =>
if (lhs.value == 1) rhs // eq(x, 1) => x
else e
@@ -91,8 +91,8 @@ object ConstProp extends Pass {
}
object FoldNotEqual extends FoldLogicalOp {
- def fold(c1: UIntValue, c2: UIntValue) = UIntValue(if (c1.value != c2.value) 1 else 0, IntWidth(1))
- def simplify(e: Expression, lhs: UIntValue, rhs: Expression) = lhs.width match {
+ def fold(c1: UIntLiteral, c2: UIntLiteral) = UIntLiteral(if (c1.value != c2.value) 1 else 0, IntWidth(1))
+ def simplify(e: Expression, lhs: UIntLiteral, rhs: Expression) = lhs.width match {
case IntWidth(w) if w == 1 && long_BANG(tpe(rhs)) == w =>
if (lhs.value == 0) rhs // neq(x, 0) => x
else e
@@ -101,15 +101,15 @@ object ConstProp extends Pass {
}
private def foldConcat(e: DoPrim) = (e.args(0), e.args(1)) match {
- case (UIntValue(xv, IntWidth(xw)), UIntValue(yv, IntWidth(yw))) => UIntValue(xv << yw.toInt | yv, IntWidth(xw + yw))
+ case (UIntLiteral(xv, IntWidth(xw)), UIntLiteral(yv, IntWidth(yw))) => UIntLiteral(xv << yw.toInt | yv, IntWidth(xw + yw))
case _ => e
}
private def foldShiftLeft(e: DoPrim) = e.consts(0).toInt match {
case 0 => e.args(0)
case x => e.args(0) match {
- case UIntValue(v, IntWidth(w)) => UIntValue(v << x, IntWidth(w + x))
- case SIntValue(v, IntWidth(w)) => SIntValue(v << x, IntWidth(w + x))
+ case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v << x, IntWidth(w + x))
+ case SIntLiteral(v, IntWidth(w)) => SIntLiteral(v << x, IntWidth(w + x))
case _ => e
}
}
@@ -118,9 +118,9 @@ object ConstProp extends Pass {
case 0 => e.args(0)
case x => e.args(0) match {
// TODO when amount >= x.width, return a zero-width wire
- case UIntValue(v, IntWidth(w)) => UIntValue(v >> x, IntWidth((w - x) max 1))
+ case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v >> x, IntWidth((w - x) max 1))
// take sign bit if shift amount is larger than arg width
- case SIntValue(v, IntWidth(w)) => SIntValue(v >> x, IntWidth((w - x) max 1))
+ case SIntLiteral(v, IntWidth(w)) => SIntLiteral(v >> x, IntWidth((w - x) max 1))
case _ => e
}
}
@@ -208,15 +208,15 @@ object ConstProp extends Pass {
case NEQUAL_OP => FoldNotEqual(e)
case LESS_OP|LESS_EQ_OP|GREATER_OP|GREATER_EQ_OP => foldComparison(e)
case NOT_OP => e.args(0) match {
- case UIntValue(v, IntWidth(w)) => UIntValue(v ^ ((BigInt(1) << w.toInt) - 1), IntWidth(w))
+ case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v ^ ((BigInt(1) << w.toInt) - 1), IntWidth(w))
case _ => e
}
case BITS_SELECT_OP => e.args(0) match {
- case UIntValue(v, _) => {
+ case UIntLiteral(v, _) => {
val hi = e.consts(0).toInt
val lo = e.consts(1).toInt
require(hi >= lo)
- UIntValue((v >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(tpe(e)))
+ UIntLiteral((v >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(tpe(e)))
}
case x if long_BANG(tpe(e)) == long_BANG(tpe(x)) => tpe(x) match {
case t: UIntType => x
@@ -230,28 +230,28 @@ object ConstProp extends Pass {
private def constPropMuxCond(m: Mux) = {
// Only propagate a value if its width matches the mux width
def propagate(e: Expression, muxWidth: BigInt) = e match {
- case UIntValue(v, _) => UIntValue(v, IntWidth(muxWidth))
+ case UIntLiteral(v, _) => UIntLiteral(v, IntWidth(muxWidth))
case _ => tpe(e) match {
case UIntType(IntWidth(w)) if muxWidth == w => e
case _ => m
}
}
(m.cond, m.tpe) match {
- case (UIntValue(c, _), UIntType(IntWidth(w))) => propagate(if (c == 1) m.tval else m.fval, w)
+ case (UIntLiteral(c, _), UIntType(IntWidth(w))) => propagate(if (c == 1) m.tval else m.fval, w)
case _ => m
}
}
private def constPropMux(m: Mux): Expression = (m.tval, m.fval) match {
case _ if m.tval == m.fval => m.tval
- case (t: UIntValue, f: UIntValue) =>
+ case (t: UIntLiteral, f: UIntLiteral) =>
if (t.value == 1 && f.value == 0 && long_BANG(m.tpe) == 1) m.cond
else constPropMuxCond(m)
case _ => constPropMuxCond(m)
}
private def constPropNodeRef(r: WRef, e: Expression) = e match {
- case _: UIntValue | _: SIntValue | _: WRef => e
+ case _: UIntLiteral | _: SIntLiteral | _: WRef => e
case _ => r
}
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 36919756..d905fc34 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -149,7 +149,7 @@ object LowerTypes extends Pass {
}
case e: Mux => e map (lowerTypesExp)
case e: ValidIf => e map (lowerTypesExp)
- case (_: UIntValue | _: SIntValue) => e
+ case (_: UIntLiteral | _: SIntLiteral) => e
case e: DoPrim => e map (lowerTypesExp)
}
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 094166fb..ce1c7eed 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -69,10 +69,10 @@ object ToWorkingIR extends Pass {
def run (c:Circuit): Circuit = {
def toExp (e:Expression) : Expression = {
e map (toExp) match {
- case e:Ref => WRef(e.name, e.tpe, NodeKind(), UNKNOWNGENDER)
- case e:SubField => WSubField(e.exp, e.name, e.tpe, UNKNOWNGENDER)
- case e:SubIndex => WSubIndex(e.exp, e.value, e.tpe, UNKNOWNGENDER)
- case e:SubAccess => WSubAccess(e.exp, e.index, e.tpe, UNKNOWNGENDER)
+ case e:Reference => WRef(e.name, e.tpe, NodeKind(), UNKNOWNGENDER)
+ case e:SubField => WSubField(e.expr, e.name, e.tpe, UNKNOWNGENDER)
+ case e:SubIndex => WSubIndex(e.expr, e.value, e.tpe, UNKNOWNGENDER)
+ case e:SubAccess => WSubAccess(e.expr, e.index, e.tpe, UNKNOWNGENDER)
case e => e
}
}
@@ -176,8 +176,8 @@ object InferTypes extends Pass {
case e:WSubAccess => WSubAccess(e.exp,e.index,sub_type(tpe(e.exp)),e.gender)
case e:DoPrim => set_primop_type(e)
case e:Mux => Mux(e.cond,e.tval,e.fval,mux_type_and_widths(e.tval,e.fval))
- case e:UIntValue => e
- case e:SIntValue => e
+ case e:UIntLiteral => e
+ case e:SIntLiteral => e
}
}
def infer_types_s (s:Statement) : Statement = {
@@ -822,8 +822,8 @@ object RemoveAccesses extends Pass {
case (e:DoPrim) => e map (remove_e)
case (e:Mux) => e map (remove_e)
case (e:ValidIf) => e map (remove_e)
- case (e:SIntValue) => e
- case (e:UIntValue) => e
+ case (e:SIntLiteral) => e
+ case (e:UIntLiteral) => e
case x => {
val e = x match {
case (w:WSubAccess) => WSubAccess(w.exp,remove_e(w.index),w.tpe,w.gender)
@@ -900,7 +900,7 @@ object Legalize extends Pass {
lazy val msb = width - 1
if (amount >= width) {
e.tpe match {
- case t: UIntType => UIntValue(0, IntWidth(1))
+ case t: UIntType => UIntLiteral(0, IntWidth(1))
case t: SIntType =>
DoPrim(BITS_SELECT_OP, e.args, Seq(msb, msb), SIntType(IntWidth(1)))
case t => error(s"Unsupported type ${t} for Primop Shift Right")
@@ -1053,14 +1053,14 @@ object CInferTypes extends Pass {
val types = LinkedHashMap[String,Type]()
def infer_types_e (e:Expression) : Expression = {
(e map (infer_types_e)) match {
- case (e:Ref) => Ref(e.name, types.getOrElse(e.name,UnknownType))
- case (e:SubField) => SubField(e.exp,e.name,field_type(tpe(e.exp),e.name))
- case (e:SubIndex) => SubIndex(e.exp,e.value,sub_type(tpe(e.exp)))
- case (e:SubAccess) => SubAccess(e.exp,e.index,sub_type(tpe(e.exp)))
+ case (e:Reference) => Reference(e.name, types.getOrElse(e.name,UnknownType))
+ case (e:SubField) => SubField(e.expr,e.name,field_type(tpe(e.expr),e.name))
+ case (e:SubIndex) => SubIndex(e.expr,e.value,sub_type(tpe(e.expr)))
+ case (e:SubAccess) => SubAccess(e.expr,e.index,sub_type(tpe(e.expr)))
case (e:DoPrim) => set_primop_type(e)
case (e:Mux) => Mux(e.cond,e.tval,e.fval,mux_type(e.tval,e.tval))
case (e:ValidIf) => ValidIf(e.cond,e.value,tpe(e.value))
- case (_:UIntValue|_:SIntValue) => e
+ case (_:UIntLiteral | _:SIntLiteral) => e
}
}
def infer_types_s (s:Statement) : Statement = {
@@ -1126,7 +1126,7 @@ object CInferMDir extends Pass {
val mports = LinkedHashMap[String,MPortDir]()
def infer_mdir_e (dir:MPortDir)(e:Expression) : Expression = {
(e map (infer_mdir_e(dir))) match {
- case (e:Ref) => {
+ case (e:Reference) => {
if (mports.contains(e.name)) {
val new_mport_dir = {
(mports(e.name),dir) match {
@@ -1253,23 +1253,23 @@ object RemoveCHIRRTL extends Pass {
val tdata = s.tpe
def set_poison (vec:Seq[MPort],addr:String) : Unit = {
for (r <- vec ) {
- stmts += IsInvalid(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),addr,taddr))
- stmts += IsInvalid(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),"clk",taddr))
+ stmts += IsInvalid(s.info,SubField(SubField(Reference(s.name,ut),r.name,ut),addr,taddr))
+ stmts += IsInvalid(s.info,SubField(SubField(Reference(s.name,ut),r.name,ut),"clk",taddr))
}
}
def set_enable (vec:Seq[MPort],en:String) : Unit = {
for (r <- vec ) {
- stmts += Connect(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),en,taddr),zero)
+ stmts += Connect(s.info,SubField(SubField(Reference(s.name,ut),r.name,ut),en,taddr),zero)
}}
def set_wmode (vec:Seq[MPort],wmode:String) : Unit = {
for (r <- vec) {
- stmts += Connect(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),wmode,taddr),zero)
+ stmts += Connect(s.info,SubField(SubField(Reference(s.name,ut),r.name,ut),wmode,taddr),zero)
}}
def set_write (vec:Seq[MPort],data:String,mask:String) : Unit = {
val tmask = create_mask(s.tpe)
for (r <- vec ) {
- stmts += IsInvalid(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),data,tdata))
- for (x <- create_exps(SubField(SubField(Ref(s.name,ut),r.name,ut),mask,tmask)) ) {
+ stmts += IsInvalid(s.info,SubField(SubField(Reference(s.name,ut),r.name,ut),data,tdata))
+ for (x <- create_exps(SubField(SubField(Reference(s.name,ut),r.name,ut),mask,tmask)) ) {
stmts += Connect(s.info,x,zero)
}}}
val rds = (hash.getOrElse(s.name,EMPs())).readers
@@ -1296,21 +1296,21 @@ object RemoveCHIRRTL extends Pass {
val masks = ArrayBuffer[String]()
s.direction match {
case MReadWrite => {
- repl(s.name) = DataRef(SubField(Ref(s.mem,ut),s.name,ut),"rdata","data","mask",true)
+ repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"rdata","data","mask",true)
addrs += "addr"
clks += "clk"
ens += "en"
masks += "mask"
}
case MWrite => {
- repl(s.name) = DataRef(SubField(Ref(s.mem,ut),s.name,ut),"data","data","mask",false)
+ repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"data","data","mask",false)
addrs += "addr"
clks += "clk"
ens += "en"
masks += "mask"
}
case _ => {
- repl(s.name) = DataRef(SubField(Ref(s.mem,ut),s.name,ut),"data","data","blah",false)
+ repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"data","data","blah",false)
addrs += "addr"
clks += "clk"
ens += "en"
@@ -1318,13 +1318,13 @@ object RemoveCHIRRTL extends Pass {
}
val stmts = ArrayBuffer[Statement]()
for (x <- addrs ) {
- stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),s.exps(0))
+ stmts += Connect(s.info,SubField(SubField(Reference(s.mem,ut),s.name,ut),x,ut),s.exps(0))
}
for (x <- clks ) {
- stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),s.exps(1))
+ stmts += Connect(s.info,SubField(SubField(Reference(s.mem,ut),s.name,ut),x,ut),s.exps(1))
}
for (x <- ens ) {
- stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),one)
+ stmts += Connect(s.info,SubField(SubField(Reference(s.mem,ut),s.name,ut),x,ut),one)
}
Begin(stmts)
}
@@ -1336,7 +1336,7 @@ object RemoveCHIRRTL extends Pass {
var has_readwrite_mport:Option[Expression] = None
def remove_chirrtl_e (g:Gender)(e:Expression) : Expression = {
(e) match {
- case (e:Ref) => {
+ case (e:Reference) => {
if (repl.contains(e.name)) {
val vt = repl(e.name)
g match {
@@ -1350,13 +1350,13 @@ object RemoveCHIRRTL extends Pass {
}
} else e
}
- case (e:SubAccess) => SubAccess(remove_chirrtl_e(g)(e.exp),remove_chirrtl_e(MALE)(e.index),e.tpe)
+ case (e:SubAccess) => SubAccess(remove_chirrtl_e(g)(e.expr),remove_chirrtl_e(MALE)(e.index),e.tpe)
case (e) => e map (remove_chirrtl_e(g))
}
}
def get_mask (e:Expression) : Expression = {
(e map (get_mask)) match {
- case (e:Ref) => {
+ case (e:Reference) => {
if (repl.contains(e.name)) {
val vt = repl(e.name)
val t = create_mask(e.tpe)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 2fdc3454..3ad0c3dc 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -192,7 +192,7 @@ object Uniquify extends Pass {
val (subExp, subMap) = rec(e.exp, m)
val index = uniquifyNamesExp(e.index, map)
(WSubAccess(subExp, index, e.tpe, e.gender), subMap)
- case (_: UIntValue | _: SIntValue) => (exp, m)
+ case (_: UIntLiteral | _: SIntLiteral) => (exp, m)
case (_: Mux | _: ValidIf | _: DoPrim) =>
(exp map ((e: Expression) => uniquifyNamesExp(e, map)), m)
}
@@ -267,7 +267,7 @@ object Uniquify extends Pass {
uniquifyNamesExp(e, nameMap.toMap)
case e: Mux => e map (uniquifyExp)
case e: ValidIf => e map (uniquifyExp)
- case (_: UIntValue | _: SIntValue) => e
+ case (_: UIntLiteral | _: SIntLiteral) => e
case e: DoPrim => e map (uniquifyExp)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 12:14:57 +0000