diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/InferWidths.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/WidthSpec.scala | 23 |
2 files changed, 24 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala index 67f2b90e..619bb25a 100644 --- a/src/main/scala/firrtl/passes/InferWidths.scala +++ b/src/main/scala/firrtl/passes/InferWidths.scala @@ -81,7 +81,7 @@ object InferWidths extends Pass { def remove_cycle(n: String)(w: Width): Width = { //;println-all-debug(["Removing cycle for " n " inside " w]) - w map remove_cycle(n) match { + w match { case wx: MaxWidth => MaxWidth(wx.args filter { case wxx: VarWidth => !(n equals wxx.name) case _ => true diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index f2938016..9b0ee139 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -78,4 +78,27 @@ class WidthSpec extends FirrtlFlatSpec { executeTest(input, Nil, passes) } } + "Circular reg depending on reg + 1" should "error" in { + val passes = Seq( + ToWorkingIR, + CheckHighForm, + ResolveKinds, + InferTypes, + CheckTypes, + InferWidths, + CheckWidths) + val input = + """circuit Unit : + | module Unit : + | input clock: Clock + | input reset: UInt<1> + | reg r : UInt, clock with : + | reset => (reset, UInt(3)) + | node T_7 = add(r, r) + | r <= T_7 + |""".stripMargin + intercept[CheckWidths.UninferredWidth] { + executeTest(input, Nil, passes) + } + } } |