2 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 0bb7510f..34776cf3 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -40,7 +40,6 @@ trait Compiler extends LazyLogging {
 object FIRRTLCompiler extends Compiler {
   def run(c: Circuit, w: Writer) = {
     FIRRTLEmitter.run(c, w)
-    w.close
   }
 }
 
@@ -84,7 +83,6 @@ object VerilogCompiler extends Compiler {
   {
     val loweredIR = PassUtils.executePasses(c, passes)
     VerilogEmitter.run(loweredIR, w)
-    w.close
   }
 
 }
diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index c2dc0b59..1e0d9cf1 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -48,6 +48,7 @@ object Driver extends LazyLogging {
     val parsedInput = Parser.parse(input, Source.fromFile(input).getLines)
     val writerOutput = new PrintWriter(new File(output))
     compiler.run(parsedInput, writerOutput)
+    writerOutput.close
   }
 
   def main(args: Array[String])