diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 10 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index fdfda3e6..850c8ca1 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -398,7 +398,7 @@ class VerilogEmitter extends SeqTransform with Emitter { error("Verilog emitter does not support SHIFT_RIGHT >= arg width") case Shr if c0 == (bitWidth(a0.tpe)-1) => Seq(a0,"[", bitWidth(a0.tpe) - 1, "]") case Shr => Seq(a0,"[", bitWidth(a0.tpe) - 1, ":", c0, "]") - case Neg => Seq("-{", cast(a0), "}") + case Neg => Seq("-", cast(a0)) case Cvt => a0.tpe match { case (_: UIntType) => Seq("{1'b0,", cast(a0), "}") case (_: SIntType) => Seq(cast(a0)) diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 653653d6..efe85e48 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1651,4 +1651,14 @@ class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec { |""".stripMargin firrtlEquivalenceTest(input, transforms) } + + "propagation of signed expressions" should "have the correct signs" in { + val input = + s"""circuit SignTester : + | module SignTester : + | output ref : SInt<3> + | ref <= mux(UInt<1>("h0"), SInt<3>("h0"), neg(UInt<2>("h3"))) + |""".stripMargin + firrtlEquivalenceTest(input, transforms) + } } |