diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 5 | ||||
| -rw-r--r-- | src/main/stanza/errors.stanza | 8 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 3 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index e8c0acc8..01f6db96 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -54,10 +54,10 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : CInferMDir() RemoveCHIRRTL() ;=============== - CheckHighForm() - ;=============== ToWorkingIR() ;=============== + CheckHighForm() + ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -115,7 +115,6 @@ public defmethod backend (c:StandardFIRRTL) -> List<Pass> : to-list $ [ FIRRTL(with-output(c)) ] public defmethod passes (c:StandardFIRRTL) -> List<Pass> : to-list $ [ - CheckHighForm() FIRRTL(with-output(c)) ] diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index a0c48dc8..92f1b97e 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -257,17 +257,17 @@ public defn check-high-form (c:Circuit) -> Circuit : defn check-high-form-e (e:Expression) -> Expression : defn valid-subexp (e:Expression) -> Expression : match(e) : - (e:Ref|SubField|SubIndex|SubAccess|Mux|ValidIf) : false + (e:WRef|WSubField|WSubIndex|WSubAccess|Mux|ValidIf) : false (e) : add(errors,InvalidAccess()) e match(map(check-high-form-e,e)) : - (e:Ref) : + (e:WRef) : if not key?(names,name(e)) : add(errors,UndeclaredReference(name(e))) (e:DoPrim) : check-high-form-primop(e) (e:Mux|ValidIf) : e (e:UIntValue) : false - (e:SubAccess) : + (e:WSubAccess) : valid-subexp(exp(e)) e (e) : map(valid-subexp,e) @@ -293,7 +293,7 @@ public defn check-high-form (c:Circuit) -> Circuit : (s:DefMemory) : if has-flip?(data-type(s)) : add(errors, MemWithFlip(name(s))) if depth(s) <= 0 : add(errors,NegMemSize()) - (s:DefInstance) : + (s:WDefInstance) : if not contains?(module(s),map(name,modules(c))) : add(errors, ModuleNotDefined(module(s))) (s:Connect) : check-valid-loc(loc(s)) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 3e90b502..155c1b0a 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -24,6 +24,7 @@ public val standard-passes = to-list $ [ ExpandConnects() RemoveAccesses() ExpandWhens() + LowerTypes() CheckInitialization() ConstProp() VerilogWrap() @@ -2879,7 +2880,7 @@ defn emit-verilog (with-output:(() -> False) -> False, c:Circuit) : public defstruct LoToVerilog <: Pass : with-output: (() -> False) -> False public defmethod pass (b:LoToVerilog) -> (Circuit -> Circuit) : lo-to-verilog{with-output(b),_} -public defmethod name (b:LoToVerilog) -> String : "To LoToVerilog" +public defmethod name (b:LoToVerilog) -> String : "Lo To Verilog" public defmethod short-name (b:LoToVerilog) -> String : "lo-to-verilog" defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) : |