diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 1 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/CompilerTests.scala | 15 |
2 files changed, 7 insertions, 9 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 7499d6d1..9969150d 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -119,6 +119,7 @@ class MinimumLowFirrtlOptimization extends CoreTransform { def inputForm = LowForm def outputForm = LowForm def transforms = Seq( + passes.RemoveValidIf, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.SplitExpressions) diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index ff7d2cb8..df83dd38 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -159,21 +159,18 @@ class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers { val input = """|circuit Top: | module Top: | output b: UInt<1>[2] - | node c = UInt<1>("h0") - | node d = UInt<1>("h0") - | b[0] <= UInt<1>("h0") - | b[1] <= c + | node c = UInt<1>("h1") + | b[0] <= c + | b[1] is invalid |""".stripMargin val check = """|module Top( | output b_0, | output b_1 |); | wire c; - | wire d; - | assign c = 1'h0; - | assign d = 1'h0; - | assign b_0 = 1'h0; - | assign b_1 = c; + | assign c = 1'h1; + | assign b_0 = c; + | assign b_1 = 1'h0; |endmodule |""".stripMargin def compiler = new MinimumVerilogCompiler() |