2 files changed, 53 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/annotations/Target.scala b/src/main/scala/firrtl/annotations/Target.scala
index dcf5cb02..8a9d68e8 100644
--- a/src/main/scala/firrtl/annotations/Target.scala
+++ b/src/main/scala/firrtl/annotations/Target.scala
@@ -55,6 +55,32 @@ sealed trait Target extends Named {
     }
   }
 
+  /** Pretty serialization, ideal for error messages. Cannot be deserialized.
+    * @return Human-readable serialization
+    */
+  def prettyPrint(tab: String = ""): String = {
+    val circuitString = s"""${tab}circuit ${circuitOpt.getOrElse("???")}:"""
+    val moduleString = s"""\n$tab└── module ${moduleOpt.getOrElse("???")}:"""
+    var depth = 4
+    val tokenString = tokens.map {
+      case Ref(r) => val rx = s"""\n$tab${" "*depth}└── $r"""; depth += 4; rx
+      case Instance(i) => val ix = s"""\n$tab${" "*depth}└── inst $i """; ix
+      case OfModule(o) => val ox = s"of $o:"; depth += 4; ox
+      case Field(f) => s".$f"
+      case Index(v) => s"[$v]"
+      case Clock => s"@clock"
+      case Reset => s"@reset"
+      case Init => s"@init"
+    }.mkString("")
+
+    (moduleOpt.isEmpty, tokens.isEmpty) match {
+      case (true, true) => circuitString
+      case (_, true) => circuitString + moduleString
+      case (_, _) => circuitString + moduleString + tokenString
+    }
+  }
+
+
   /** @return Converts this [[Target]] into a [[GenericTarget]] */
   def toGenericTarget: GenericTarget = GenericTarget(circuitOpt, moduleOpt, tokens.toVector)
 
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
index 4ae4e036..da154b6a 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
@@ -55,5 +55,31 @@ class TargetSpec extends FirrtlPropSpec {
       assert(Target.deserialize(t.serialize) == t, s"$t does not properly serialize/deserialize")
     }
   }
+  property("Pretty Printer should work") {
+    val circuit = CircuitTarget("A")
+    val top = circuit.module("B")
+    val targets = Seq(
+      (circuit, "circuit A:"),
+      (top,
+       """|circuit A:
+          |└── module B:""".stripMargin),
+      (top.instOf("c", "C"),
+       """|circuit A:
+          |└── module B:
+          |    └── inst c of C:""".stripMargin),
+      (top.ref("r"),
+       """|circuit A:
+          |└── module B:
+          |    └── r""".stripMargin),
+      (top.ref("r").index(1).field("hi").clock,
+       """|circuit A:
+          |└── module B:
+          |    └── r[1].hi@clock""".stripMargin),
+      (GenericTarget(None, None, Vector(Ref("r"))),
+       """|circuit ???:
+          |└── module ???:
+          |    └── r""".stripMargin)
+    )
+    targets.foreach { case (t, str) => assert(t.prettyPrint() == str, s"$t didn't properly prettyPrint") }
+  }
 }
-