diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index c8430d2b..4d40d9a8 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -124,7 +124,6 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun { val passSeq = Seq( - passes.Legalize, passes.LowerTypes, passes.ResolveKinds, passes.InferTypes, @@ -146,6 +145,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl passes.ConstProp, passes.PadWidths, passes.ConstProp, + passes.Legalize, passes.VerilogWrap, passes.SplitExpressions, passes.CommonSubexpressionElimination, diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 0405701f..66437556 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -228,6 +228,16 @@ object Legalize extends Pass { e } } + private def legalizeBits(expr: DoPrim): Expression = { + lazy val (hi, low) = (expr.consts(0), expr.consts(1)) + lazy val mask = (BigInt(1) << (hi - low + 1).toInt) - 1 + lazy val width = IntWidth(hi - low + 1) + expr.args.head match { + case UIntLiteral(value, _) => UIntLiteral((value >> low.toInt) & mask, width) + case SIntLiteral(value, _) => SIntLiteral((value >> low.toInt) & mask, width) + case _ => expr + } + } private def legalizeConnect(c: Connect): Statement = { val t = c.loc.tpe val w = bitWidth(t) @@ -246,6 +256,7 @@ object Legalize extends Pass { def legalizeE(expr: Expression): Expression = expr map legalizeE match { case prim: DoPrim => prim.op match { case Shr => legalizeShiftRight(prim) + case Bits => legalizeBits(prim) case _ => prim } case e => e // respect pre-order traversal |