diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 32027f67..c87928c5 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -15,7 +15,7 @@ import firrtl.PrimOps._ import firrtl.WrappedExpression._ import Utils._ import MemPortUtils.{memPortField, memType} -import firrtl.options.{HasShellOptions, ShellOption, StageUtils, PhaseException} +import firrtl.options.{HasShellOptions, ShellOption, StageUtils, PhaseException, Unserializable} import firrtl.stage.RunFirrtlTransformAnnotation // Datastructures import scala.collection.mutable.ArrayBuffer @@ -93,7 +93,7 @@ final case class EmittedFirrtlModule(name: String, value: String, outputSuffix: final case class EmittedVerilogModule(name: String, value: String, outputSuffix: String) extends EmittedModule /** Traits for Annotations containing emitted components */ -sealed trait EmittedAnnotation[T <: EmittedComponent] extends NoTargetAnnotation { +sealed trait EmittedAnnotation[T <: EmittedComponent] extends NoTargetAnnotation with Unserializable { val value: T } sealed trait EmittedCircuitAnnotation[T <: EmittedCircuit] extends EmittedAnnotation[T] |