diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 4 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/TopWiringTest.scala | 104 |
2 files changed, 94 insertions, 14 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 80572b30..4a6d17d4 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -36,8 +36,8 @@ case class TopWiringAnnotation(target: ComponentName, prefix: String) extends * @note This *does* work for deduped modules */ class TopWiringTransform extends Transform { - def inputForm: CircuitForm = LowForm - def outputForm: CircuitForm = LowForm + def inputForm: CircuitForm = MidForm + def outputForm: CircuitForm = MidForm type InstPath = Seq[String] diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala index 76e5a7d5..5a6b3420 100644 --- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala +++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala @@ -23,21 +23,20 @@ import firrtl.annotations.{ import firrtl.transforms.TopWiring._ -/** - * Tests TopWiring transformation - */ -class TopWiringTests extends LowTransformSpec with FirrtlRunners { - val testDir = createTestDirectory("TopWiringTests") - val testDirName = testDir.getPath +trait TopWiringTestsCommon extends FirrtlRunners { - def topWiringDummyOutputFilesFunction(dir: String, - mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)], + val testDir = createTestDirectory("TopWiringTests") + val testDirName = testDir.getPath + def transform = new TopWiringTransform + + def topWiringDummyOutputFilesFunction(dir: String, + mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)], state: CircuitState): CircuitState = { state } - def topWiringTestOutputFilesFunction(dir: String, - mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)], + def topWiringTestOutputFilesFunction(dir: String, + mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)], state: CircuitState): CircuitState = { val testOutputFile = new PrintWriter(new File(dir, "TopWiringOutputTest.txt" )) mapping map { @@ -51,8 +50,13 @@ class TopWiringTests extends LowTransformSpec with FirrtlRunners { testOutputFile.close() state } +} + +/** + * Tests TopWiring transformation + */ +class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { - def transform = new TopWiringTransform "The signal x in module C" should s"be connected to Top port with topwiring prefix and outputfile in $testDirName" in { val input = """circuit Top : @@ -594,7 +598,6 @@ class TopWiringTests extends LowTransformSpec with FirrtlRunners { execute(input, check, topwiringannos) } - "TopWiringTransform" should "do nothing if run without TopWiring* annotations" in { val input = """|circuit Top : | module Top : @@ -619,3 +622,80 @@ class TopWiringTests extends LowTransformSpec with FirrtlRunners { } } } + +class AggregateTopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon { + + "An aggregate wire named myAgg in A" should s"be wired to Top's IO as topwiring_a1_myAgg" in { + val input = + """circuit Top : + | module Top : + | inst a1 of A + | module A: + | wire myAgg: { a: UInt<1>, b: SInt<8> } + | myAgg.a <= UInt(0) + | myAgg.b <= SInt(-1) + """.stripMargin + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"myAgg", ModuleName(s"A", CircuitName(s"Top"))), + s"topwiring_")) + val check = + """circuit Top : + | module Top : + | output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> } + | inst a1 of A + | topwiring_a1_myAgg <= a1.topwiring_myAgg + | module A : + | output topwiring_myAgg: { a: UInt<1>, b: SInt<8> } + | wire myAgg: { a: UInt<1>, b: SInt<8> } + | myAgg.a <= UInt(0) + | myAgg.b <= SInt(-1) + | topwiring_myAgg <= myAgg + """.stripMargin + execute(input, check, topwiringannos) + } + + "Aggregate wires myAgg in Top.a1, Top.b.a1 and Top.b.a2" should + s"be wired to Top's IO as topwiring_a1_myAgg, topwiring_b_a1_myAgg, and topwiring_b_a2_myAgg" in { + val input = + """circuit Top : + | module Top : + | inst a1 of A + | inst b of B + | module B: + | inst a1 of A + | inst a2 of A + | module A: + | wire myAgg: { a: UInt<1>, b: SInt<8> } + | myAgg.a <= UInt(0) + | myAgg.b <= SInt(-1) + """.stripMargin + val topwiringannos = Seq( + TopWiringAnnotation(ComponentName(s"myAgg", ModuleName(s"A", CircuitName(s"Top"))), s"topwiring_")) + + val check = + """circuit Top : + | module Top : + | output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> } + | output topwiring_b_a1_myAgg: { a: UInt<1>, b: SInt<8> } + | output topwiring_b_a2_myAgg: { a: UInt<1>, b: SInt<8> } + | inst a1 of A + | inst b of B + | topwiring_a1_myAgg <= a1.topwiring_myAgg + | topwiring_b_a1_myAgg <= b.topwiring_a1_myAgg + | topwiring_b_a2_myAgg <= b.topwiring_a2_myAgg + | module B: + | output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> } + | output topwiring_a2_myAgg: { a: UInt<1>, b: SInt<8> } + | inst a1 of A + | inst a2 of A + | topwiring_a1_myAgg <= a1.topwiring_myAgg + | topwiring_a2_myAgg <= a2.topwiring_myAgg + | module A : + | output topwiring_myAgg: { a: UInt<1>, b: SInt<8> } + | wire myAgg: { a: UInt<1>, b: SInt<8> } + | myAgg.a <= UInt(0) + | myAgg.b <= SInt(-1) + | topwiring_myAgg <= myAgg + """.stripMargin + execute(input, check, topwiringannos) + } +} |