diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 316a7044..30c764d8 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -316,7 +316,7 @@ class VerilogEmitter extends Emitter { assigns += Seq("assign ",e," = ",value,";") // In simulation, assign garbage under a predicate def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression) = { - assigns += Seq("`ifndef RANDOMIZE") + assigns += Seq("`ifndef RANDOMIZE_ASSIGN") assigns += Seq("assign ", e, " = ", syn, ";") assigns += Seq("`else") assigns += Seq("assign ", e, " = ", garbageCond, " ? ", rand_string(tpe(syn)), " : ", syn, ";") @@ -381,14 +381,14 @@ class VerilogEmitter extends Emitter { Seq(nx,"[",long_BANG(t) - 1,":0]") } def initialize(e: Expression) = { - initials += Seq("`ifdef RANDOMIZE") + initials += Seq("`ifdef RANDOMIZE_REG_INIT") initials += Seq(e, " = ", rand_string(tpe(e)), ";") initials += Seq("`endif") } def initialize_mem(s: DefMemory) = { val index = WRef("initvar", s.dataType, ExpKind(), UNKNOWNGENDER) val rstring = rand_string(s.dataType) - initials += Seq("`ifdef RANDOMIZE") + initials += Seq("`ifdef RANDOMIZE_MEM_INIT") initials += Seq("for (initvar = 0; initvar < ", s.depth, "; initvar = initvar+1)") initials += Seq(tab, WSubAccess(wref(s.name, s.dataType), index, s.dataType, FEMALE), " = ", rstring,";") initials += Seq("`endif") @@ -673,16 +673,30 @@ class VerilogEmitter extends Emitter { emit(Seq("endmodule")) } - + build_netlist(m.body) build_ports() build_streams(m.body) emit_streams() m } - + + def emit_preamble() { + emit(Seq( + "`ifdef RANDOMIZE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n")) + } + def run(c: Circuit, w: Writer) = { this.w = Some(w) + emit_preamble() for (m <- c.modules) { m match { case (m:Module) => emit_verilog(m) |