diff options
Diffstat (limited to 'src')
5 files changed, 37 insertions, 40 deletions
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala index c8b83bd2..aeefbbe3 100644 --- a/src/test/scala/firrtlTests/AnnotationTests.scala +++ b/src/test/scala/firrtlTests/AnnotationTests.scala @@ -23,13 +23,13 @@ trait AnnotationSpec extends LowTransformSpec { def transform = new ResolveAndCheck // Check if Annotation Exception is thrown - override def failingexecute(annotations: AnnotationMap, input: String): Exception = { + override def failingexecute(input: String, annotations: Seq[Annotation]): Exception = { intercept[AnnotationException] { - compile(CircuitState(parse(input), ChirrtlForm, Some(annotations)), Seq.empty) + compile(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations))), Seq.empty) } } - def execute(aMap: Option[AnnotationMap], input: String, check: Annotation): Unit = { - val cr = compile(CircuitState(parse(input), ChirrtlForm, aMap), Seq.empty) + def execute(input: String, check: Annotation, annotations: Seq[Annotation]): Unit = { + val cr = compile(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations))), Seq.empty) cr.annotations.get.annotations should contain (check) } } @@ -58,7 +58,7 @@ class AnnotationTests extends AnnotationSpec with Matchers { | input b : UInt<1> | node c = b""".stripMargin val ta = anno("c", "") - execute(getAMap(ta), input, ta) + execute(input, ta, Seq(ta)) } "Annotations" should "be readable from file" in { diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala index 9e8f8054..4398df48 100644 --- a/src/test/scala/firrtlTests/InlineInstancesTests.scala +++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala @@ -6,7 +6,7 @@ import org.scalatest.FlatSpec import org.scalatest.Matchers import org.scalatest.junit.JUnitRunner import firrtl.ir.Circuit -import firrtl.{AnnotationMap, Parser} +import firrtl.Parser import firrtl.passes.PassExceptions import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName, Named} import firrtl.passes.{InlineAnnotation, InlineInstances} @@ -18,7 +18,14 @@ import logger.LogLevel.Debug * Tests inline instances transformation */ class InlineInstancesTests extends LowTransformSpec { - def transform = new InlineInstances + def transform = new InlineInstances + def inline(mod: String): Annotation = { + val parts = mod.split('.') + val modName = ModuleName(parts.head, CircuitName("Top")) // If this fails, bad input + val name = if (parts.size == 1) modName + else ComponentName(parts.tail.mkString("."), modName) + InlineAnnotation(name) + } // Set this to debug, this will apply to all tests // Logger.setLevel(this.getClass, Debug) "The module Inline" should "be inlined" in { @@ -44,8 +51,7 @@ class InlineInstancesTests extends LowTransformSpec { | i$b <= i$a | b <= i$b | i$a <= a""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("Inline", CircuitName("Top"))))) - execute(aMap, input, check) + execute(input, check, Seq(inline("Inline"))) } "The all instances of Simple" should "be inlined" in { @@ -77,8 +83,7 @@ class InlineInstancesTests extends LowTransformSpec { | b <= i1$b | i0$a <= a | i1$a <= i0$b""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("Simple", CircuitName("Top"))))) - execute(aMap, input, check) + execute(input, check, Seq(inline("Simple"))) } "Only one instance of Simple" should "be inlined" in { @@ -112,8 +117,7 @@ class InlineInstancesTests extends LowTransformSpec { | input a : UInt<32> | output b : UInt<32> | b <= a""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ComponentName("i0",ModuleName("Top", CircuitName("Top")))))) - execute(aMap, input, check) + execute(input, check, Seq(inline("Top.i0"))) } "All instances of A" should "be inlined" in { @@ -157,8 +161,7 @@ class InlineInstancesTests extends LowTransformSpec { | i$b <= i$a | b <= i$b | i$a <= a""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top"))))) - execute(aMap, input, check) + execute(input, check, Seq(inline("A"))) } "Non-inlined instances" should "still prepend prefix" in { @@ -196,8 +199,7 @@ class InlineInstancesTests extends LowTransformSpec { | input a : UInt<32> | output b : UInt<32> | b <= a""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top"))))) - execute(aMap, input, check) + execute(input, check, Seq(inline("A"))) } // ---- Errors ---- @@ -214,8 +216,7 @@ class InlineInstancesTests extends LowTransformSpec { | extmodule A : | input a : UInt<32> | output b : UInt<32>""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top"))))) - failingexecute(aMap, input) + failingexecute(input, Seq(inline("A"))) } // 2) ext instance "External instance" should "not be inlined" in { @@ -230,8 +231,7 @@ class InlineInstancesTests extends LowTransformSpec { | extmodule A : | input a : UInt<32> | output b : UInt<32>""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top"))))) - failingexecute(aMap, input) + failingexecute(input, Seq(inline("A"))) } // 3) no module "Inlined module" should "exist" in { @@ -241,8 +241,7 @@ class InlineInstancesTests extends LowTransformSpec { | input a : UInt<32> | output b : UInt<32> | b <= a""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top"))))) - failingexecute(aMap, input) + failingexecute(input, Seq(inline("A"))) } // 4) no inst "Inlined instance" should "exist" in { @@ -252,8 +251,7 @@ class InlineInstancesTests extends LowTransformSpec { | input a : UInt<32> | output b : UInt<32> | b <= a""".stripMargin - val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top"))))) - failingexecute(aMap, input) + failingexecute(input, Seq(inline("A"))) } } diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala index 7fa7e8ef..6727533e 100644 --- a/src/test/scala/firrtlTests/PassTests.scala +++ b/src/test/scala/firrtlTests/PassTests.scala @@ -9,6 +9,7 @@ import firrtl.ir.Circuit import firrtl.Parser.UseInfo import firrtl.passes.{Pass, PassExceptions, RemoveEmpty} import firrtl._ +import firrtl.annotations._ import logger._ // An example methodology for testing Firrtl Passes @@ -18,8 +19,9 @@ abstract class SimpleTransformSpec extends FlatSpec with FirrtlMatchers with Com def squash(c: Circuit): Circuit = RemoveEmpty.run(c) // Executes the test. Call in tests. - def execute(annotations: AnnotationMap, input: String, check: String): Unit = { - val finalState = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotations))) + // annotations cannot have default value because scalatest trait Suite has a default value + def execute(input: String, check: String, annotations: Seq[Annotation]): Unit = { + val finalState = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations)))) val actual = RemoveEmpty.run(parse(finalState.getEmittedCircuit.value)).serialize val expected = parse(check).serialize logger.debug(actual) @@ -27,9 +29,10 @@ abstract class SimpleTransformSpec extends FlatSpec with FirrtlMatchers with Com (actual) should be (expected) } // Executes the test, should throw an error - def failingexecute(annotations: AnnotationMap, input: String): Exception = { + // No default to be consistent with execute + def failingexecute(input: String, annotations: Seq[Annotation]): Exception = { intercept[PassExceptions] { - compile(CircuitState(parse(input), ChirrtlForm, Some(annotations)), Seq.empty) + compile(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations))), Seq.empty) } } } diff --git a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala index 8cd51b2a..bf294fe9 100644 --- a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala +++ b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala @@ -78,12 +78,12 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec { "annotated external modules" should "appear in output directory" in { - val aMap = AnnotationMap(Seq( + val annos = Seq( Annotation(moduleName, classOf[BlackBoxSourceHelper], BlackBoxTargetDir("test_run_dir").serialize), Annotation(moduleName, classOf[BlackBoxSourceHelper], BlackBoxResource("/blackboxes/AdderExtModule.v").serialize) - )) + ) - execute(aMap, input, output) + execute(input, output, annos) new java.io.File("test_run_dir/AdderExtModule.v").exists should be (true) new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.FileListName}").exists should be (true) diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala index 7148dd11..74c4b4e7 100644 --- a/src/test/scala/firrtlTests/transforms/DedupTests.scala +++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala @@ -46,8 +46,7 @@ class DedupModuleTests extends HighTransformSpec { | output x: UInt<1> | x <= UInt(1) """.stripMargin - val aMap = new AnnotationMap(Nil) - execute(aMap, input, check) + execute(input, check, Seq.empty) } "The module A and B" should "be deduped" in { val input = @@ -83,8 +82,7 @@ class DedupModuleTests extends HighTransformSpec { | output x: UInt<1> | x <= UInt(1) """.stripMargin - val aMap = new AnnotationMap(Nil) - execute(aMap, input, check) + execute(input, check, Seq.empty) } "The module A and B with comments" should "be deduped" in { val input = @@ -120,8 +118,7 @@ class DedupModuleTests extends HighTransformSpec { | output x: UInt<1> | x <= UInt(1) """.stripMargin - val aMap = new AnnotationMap(Nil) - execute(aMap, input, check) + execute(input, check, Seq.empty) } "The module B, but not A, with comments" should "be deduped if not annotated" in { val input = @@ -148,8 +145,7 @@ class DedupModuleTests extends HighTransformSpec { | output x: UInt<1> @[xx 1:1] | x <= UInt(1) """.stripMargin - val aMap = new AnnotationMap(Seq(NoDedupAnnotation(ModuleName("A", CircuitName("Top"))))) - execute(aMap, input, check) + execute(input, check, Seq(dontDedup("A"))) } } |