diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/passes.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 000419cc..35165abc 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2392,7 +2392,7 @@ defn emit-verilog (m:InModule) -> Module : (t:VectorType) : add(declares,[b " " type(t) " " n " [0:" size(t) - 1 "];"]) (t) : add(declares,[b " " t " " n ";"]) defn assign (e:Expression,value:Expression) : - add(assigns,["assign " e " = " value]) + add(assigns,["assign " e " = " value ";"]) defn update-and-reset (r:Expression,clk:Expression,reset?:Expression,init:Expression) : if not key?(at-clock,clk) : at-clock[clk] = Vector<Streamable>() |