3 files changed, 34 insertions, 13 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 383d4df7..be70ac77 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -62,6 +62,20 @@ object Utils extends LazyLogging {
     result
   }
 
+  /** Removes all [[firrtl.ir.Empty]] statements and condenses
+   * [[firrtl.ir.Block]] statements.
+    */
+  def squashEmpty(s: Statement): Statement = s map squashEmpty match {
+    case Block(stmts) =>
+      val newStmts = stmts filter (_ != EmptyStmt)
+      newStmts.size match {
+        case 0 => EmptyStmt
+        case 1 => newStmts.head
+        case _ => Block(newStmts)
+      }
+    case s => s
+  }
+
   /** Indent the results of [[ir.FirrtlNode.serialize]] */
   def indent(str: String) = str replaceAllLiterally ("\n", "\n  ")
   def serialize(bi: BigInt): String =
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 6df7664b..921693c7 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -71,18 +71,6 @@ object ExpandWhens extends Pass {
     }
     expsx
   }
-  private def squashEmpty(s: Statement): Statement = {
-    s map squashEmpty match {
-      case Block(stmts) =>
-        val newStmts = stmts filter (_ != EmptyStmt)
-        newStmts.size match {
-          case 0 => EmptyStmt
-          case 1 => newStmts.head
-          case _ => Block(newStmts)
-        }
-      case s => s
-    }
-  }
   private def expandNetlist(netlist: LinkedHashMap[WrappedExpression, Expression]) =
     netlist map { case (k, v) =>
       v match {
@@ -191,7 +179,7 @@ object ExpandWhens extends Pass {
         case m: ExtModule => m
         case m: Module =>
         val (netlist, simlist, bodyx) = expandWhens(m)
-        val newBody = Block(Seq(bodyx map squashEmpty) ++ expandNetlist(netlist) ++ simlist)
+        val newBody = Block(Seq(squashEmpty(bodyx)) ++ expandNetlist(netlist) ++ simlist)
         Module(m.info, m.name, m.ports, newBody)
       }
     }
diff --git a/src/main/scala/firrtl/passes/RemoveEmpty.scala b/src/main/scala/firrtl/passes/RemoveEmpty.scala
new file mode 100644
index 00000000..e765d1f4
--- /dev/null
+++ b/src/main/scala/firrtl/passes/RemoveEmpty.scala
@@ -0,0 +1,19 @@
+package firrtl
+package passes
+
+import scala.collection.mutable
+import firrtl.Mappers.{ExpMap, StmtMap}
+import firrtl.ir._
+
+object RemoveEmpty extends Pass {
+  def name = "Remove Empty Statements"
+  private def onModule(m: DefModule): DefModule = {
+    m match {
+      case m: Module => Module(m.info, m.name, m.ports, Utils.squashEmpty(m.body))
+      case m: ExtModule => m
+    }
+  }
+  def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main)
+}
+
+// vim: set ts=4 sw=4 et: