diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/Wiring.scala | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala index a268dba7..8c401753 100644 --- a/src/main/scala/firrtl/passes/wiring/Wiring.scala +++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala @@ -194,8 +194,12 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { Connect(NoInfo, toExp(l), toExp(r)) }) m match { - case Module(i, n, ps, s) => Module(i, n, ps ++ ports, - Block(defines ++ Seq(s) ++ connects)) + case Module(i, n, ps, body) => + val stmts = body match { + case Block(sx) => sx + case s => Seq(s) + } + Module(i, n, ps ++ ports, Block(defines ++ stmts ++ connects)) case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps ++ ports, dn, p) } } |
