aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/passes/memlib/MemConf.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemConf.scala b/src/main/scala/firrtl/passes/memlib/MemConf.scala
index 75e6b910..4d6ba2c6 100644
--- a/src/main/scala/firrtl/passes/memlib/MemConf.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemConf.scala
@@ -50,7 +50,7 @@ object MemConf {
def fromString(s: String): Seq[MemConf] = {
s.split("\n").toSeq.map(_ match {
- case MemConf.regex(name, depth, width, ports, maskGran) => Some(MemConf(name, depth.toInt, width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt)))
+ case MemConf.regex(name, depth, width, ports, maskGran) => Some(MemConf(name, BigInt(depth), width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt)))
case "" => None
case _ => throw new Exception(s"Error parsing MemConf string : ${s}")
}).flatten