diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/firrtlTests/ParserSpec.scala | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala index cd9bfb40..b030be8e 100644 --- a/src/test/scala/firrtlTests/ParserSpec.scala +++ b/src/test/scala/firrtlTests/ParserSpec.scala @@ -27,6 +27,7 @@ class ParserSpec extends FirrtlFlatSpec { val prelude = Seq("circuit top :", " module top :") val reg = " reg r : UInt<32>, clock" val reset = "reset => (radReset, UInt(\"hdeadbeef\"))" + val finfo = "@[Reg.scala:33:10]" } private object KeywordTests { @@ -77,6 +78,16 @@ class ParserSpec extends FirrtlFlatSpec { firrtl.Parser.parse((prelude :+ s"${reg} with :\n (${reset})")) } + it should "allow source locators with same-line reset" in { + import RegTests._ + firrtl.Parser.parse((prelude :+ s"${reg} with : (${reset}) $finfo" :+ " wire a : UInt")) + } + + it should "allow source locators with multi-line reset" in { + import RegTests._ + firrtl.Parser.parse((prelude :+ s"${reg} with :\n (${reset}) $finfo")) + } + // ********** Keywords ********** "Keywords" should "be allowed as Ids" in { import KeywordTests._ |
