diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 804c899a..c6bf2121 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -477,7 +477,6 @@ class VerilogEmitter extends Emitter { } case (s:Stop) => { val errorString = StringLit(s"${s.ret}\n".getBytes) - build_streams(Print(NoInfo, errorString, Seq(), s.clk, s.en)) simulate(s.clk, s.en, stop(s.ret), Some("STOP_COND")) } case (s:Print) => simulate(s.clk, s.en, printf(s.string, s.args), Some("PRINTF_COND")) |