1 files changed, 34 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index f8af4943..a2968ac5 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -30,8 +30,8 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser,Circuit,FIRRTLEmitter}
-import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,ExpandConnects,PassExceptions}
+import firrtl._
+import firrtl.passes._
 
 class UnitTests extends FlatSpec with Matchers {
   def parse (input:String) = Parser.parse("",input.split("\n").toIterator,false)
@@ -104,4 +104,36 @@ class UnitTests extends FlatSpec with Matchers {
     FIRRTLEmitter.run(c_result,writer)
     (parse(writer.toString())) should be (parse(check))
   }
+
+  val splitExpTestCode =
+     """
+       |circuit Unit :
+       |  module Unit :
+       |    input a : UInt<1>
+       |    input b : UInt<2>
+       |    input c : UInt<2>
+       |    output out : UInt<1>
+       |    out <= bits(mux(a, b, c), 0, 0)
+       |""".stripMargin
+
+  "Emitting a nested expression" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      InferTypes)
+    intercept[PassException] {
+      val c = Parser.parse("",splitExpTestCode.split("\n").toIterator)
+      val c2 = passes.foldLeft(c)((c, p) => p run c)
+      new VerilogEmitter().run(c2, new OutputStreamWriter(new ByteArrayOutputStream))
+    }
+  }
+
+  "After splitting, emitting a nested expression" should "compile" in {
+    val passes = Seq(
+      ToWorkingIR,
+      SplitExp,
+      InferTypes)
+    val c = Parser.parse("",splitExpTestCode.split("\n").toIterator)
+    val c2 = passes.foldLeft(c)((c, p) => p run c)
+    new VerilogEmitter().run(c2, new OutputStreamWriter(new ByteArrayOutputStream))
+  }
 }