diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/VerilogMemDelays.scala index 99f5b071..f6177606 100644 --- a/src/main/scala/firrtl/passes/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/VerilogMemDelays.scala @@ -39,7 +39,7 @@ object VerilogMemDelays extends Pass { def name = "Verilog Memory Delays" val ug = UNKNOWNGENDER type Netlist = collection.mutable.HashMap[String, Expression] - implicit def expToString(e: Expression) = e.serialize + implicit def expToString(e: Expression): String = e.serialize private def NOT(e: Expression) = DoPrim(Not, Seq(e), Nil, BoolType) private def AND(e1: Expression, e2: Expression) = DoPrim(And, Seq(e1, e2), Nil, BoolType) |