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-rw-r--r--src/main/scala/firrtl/Emitter.scala29
-rw-r--r--src/main/scala/firrtl/PrimOps.scala4
-rw-r--r--src/main/scala/firrtl/Utils.scala16
-rw-r--r--src/main/scala/firrtl/passes/Checks.scala12
-rw-r--r--src/main/scala/firrtl/passes/ConstProp.scala18
-rw-r--r--src/main/scala/firrtl/passes/InferWidths.scala20
-rw-r--r--src/main/scala/firrtl/passes/MemUtils.scala8
-rw-r--r--src/main/scala/firrtl/passes/PadWidths.scala3
8 files changed, 51 insertions, 59 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index e8423dfe..0af002b2 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -112,10 +112,10 @@ class VerilogEmitter extends Emitter {
case (e: Literal) => v_print(e)
case (e: VRandom) => w write s"{${e.nWords}{$$random}}"
case (t: UIntType) =>
- val wx = long_BANG(t) - 1
+ val wx = bitWidth(t) - 1
if (wx > 0) w write s"[$wx:0]"
case (t: SIntType) =>
- val wx = long_BANG(t) - 1
+ val wx = bitWidth(t) - 1
if (wx > 0) w write s"[$wx:0]"
case ClockType =>
case (t: VectorType) =>
@@ -126,6 +126,7 @@ class VerilogEmitter extends Emitter {
case (s: String) => w write s
case (i: Int) => w write i.toString
case (i: Long) => w write i.toString
+ case (i: BigInt) => w write i.toString
case (t: VIndent) => w write " "
case (s: Seq[Any]) =>
s foreach (emit(_, top + 1))
@@ -189,7 +190,7 @@ class VerilogEmitter extends Emitter {
case Eq => Seq(cast_if(a0), " == ", cast_if(a1))
case Neq => Seq(cast_if(a0), " != ", cast_if(a1))
case Pad =>
- val w = long_BANG(a0.tpe)
+ val w = bitWidth(a0.tpe)
val diff = (c0 - w)
if (w == 0) Seq(a0)
else doprim.tpe match {
@@ -210,9 +211,9 @@ class VerilogEmitter extends Emitter {
}
case Shlw => Seq(cast(a0), " << ", c0)
case Shl => Seq(cast(a0), " << ", c0)
- case Shr if c0 >= long_BANG(a0.tpe) =>
+ case Shr if c0 >= bitWidth(a0.tpe) =>
error("Verilog emitter does not support SHIFT_RIGHT >= arg width")
- case Shr => Seq(a0,"[", long_BANG(a0.tpe) - 1, ":", c0, "]")
+ case Shr => Seq(a0,"[", bitWidth(a0.tpe) - 1, ":", c0, "]")
case Neg => Seq("-{", cast(a0), "}")
case Cvt => a0.tpe match {
case (_: UIntType) => Seq("{1'b0,", cast(a0), "}")
@@ -222,24 +223,24 @@ class VerilogEmitter extends Emitter {
case And => Seq(cast_as(a0), " & ", cast_as(a1))
case Or => Seq(cast_as(a0), " | ", cast_as(a1))
case Xor => Seq(cast_as(a0), " ^ ", cast_as(a1))
- case Andr => (0 until long_BANG(doprim.tpe).toInt) map (
+ case Andr => (0 until bitWidth(doprim.tpe).toInt) map (
Seq(cast(a0), "[", _, "]")) reduce (_ + " & " + _)
- case Orr => (0 until long_BANG(doprim.tpe).toInt) map (
+ case Orr => (0 until bitWidth(doprim.tpe).toInt) map (
Seq(cast(a0), "[", _, "]")) reduce (_ + " | " + _)
- case Xorr => (0 until long_BANG(doprim.tpe).toInt) map (
+ case Xorr => (0 until bitWidth(doprim.tpe).toInt) map (
Seq(cast(a0), "[", _, "]")) reduce (_ + " ^ " + _)
case Cat => Seq("{", cast(a0), ",", cast(a1), "}")
// If selecting zeroth bit and single-bit wire, just emit the wire
- case Bits if c0 == 0 && c1 == 0 && long_BANG(a0.tpe) == 1 => Seq(a0)
+ case Bits if c0 == 0 && c1 == 0 && bitWidth(a0.tpe) == 1 => Seq(a0)
case Bits if c0 == c1 => Seq(a0, "[", c0, "]")
case Bits => Seq(a0, "[", c0, ":", c1, "]")
case Head =>
- val w = long_BANG(a0.tpe)
+ val w = bitWidth(a0.tpe)
val high = w - 1
val low = w - c0
Seq(a0, "[", high, ":", low, "]")
case Tail =>
- val w = long_BANG(a0.tpe)
+ val w = bitWidth(a0.tpe)
val low = w - c0 - 1
Seq(a0, "[", low, ":", 0, "]")
}
@@ -350,11 +351,11 @@ class VerilogEmitter extends Emitter {
// Then, return the correct number of bits selected from the random value
def rand_string(t: Type) : Seq[Any] = {
val nx = namespace.newTemp
- val rand = VRandom(long_BANG(t))
+ val rand = VRandom(bitWidth(t))
val tx = SIntType(IntWidth(rand.realWidth))
declare("reg",nx, tx)
- initials += Seq(wref(nx, tx), " = ", VRandom(long_BANG(t)), ";")
- Seq(nx, "[", long_BANG(t) - 1, ":0]")
+ initials += Seq(wref(nx, tx), " = ", VRandom(bitWidth(t)), ";")
+ Seq(nx, "[", bitWidth(t) - 1, ":0]")
}
def initialize(e: Expression) = {
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index dc6dfadb..8d677104 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -135,8 +135,8 @@ object PrimOps extends LazyLogging {
def t1 = e.args(0).tpe
def t2 = e.args(1).tpe
def t3 = e.args(2).tpe
- def w1 = Utils.width_BANG(e.args(0).tpe)
- def w2 = Utils.width_BANG(e.args(1).tpe)
+ def w1 = passes.getWidth(e.args(0).tpe)
+ def w2 = passes.getWidth(e.args(1).tpe)
def c1 = IntWidth(e.consts(0))
def c2 = IntWidth(e.consts(1))
e copy (tpe = (e.op match {
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 28f1de05..d9c74840 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -209,22 +209,6 @@ object Utils extends LazyLogging {
case v => UnknownType
}
-////=====================================
- def width_BANG(t: Type) : Width = t match {
- case g: GroundType => g.width
- case t => error("No width!")
- }
- def width_BANG(e: Expression) : Width = width_BANG(e.tpe)
- def long_BANG(t: Type): Long = t match {
- case (g: GroundType) => g.width match {
- case IntWidth(x) => x.toLong
- case _ => error(s"Expecting IntWidth, got: ${g.width}")
- }
- case (t: BundleType) => (t.fields foldLeft 0)((w, f) =>
- w + long_BANG(f.tpe).toInt)
- case (t: VectorType) => t.size * long_BANG(t.tpe)
- }
-
// =================================
def error(str: String) = throw new FIRRTLException(str)
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index bba3efe7..16b16ff7 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -572,12 +572,12 @@ object CheckWidths extends Pass {
errors append new WidthTooSmall(info, mname, e.value)
case _ =>
}
- case DoPrim(Bits, Seq(a), Seq(hi, lo), _) if long_BANG(a.tpe) <= hi =>
- errors append new BitsWidthException(info, mname, hi, long_BANG(a.tpe))
- case DoPrim(Head, Seq(a), Seq(n), _) if long_BANG(a.tpe) < n =>
- errors append new HeadWidthException(info, mname, n, long_BANG(a.tpe))
- case DoPrim(Tail, Seq(a), Seq(n), _) if long_BANG(a.tpe) <= n =>
- errors append new TailWidthException(info, mname, n, long_BANG(a.tpe))
+ case DoPrim(Bits, Seq(a), Seq(hi, lo), _) if bitWidth(a.tpe) <= hi =>
+ errors append new BitsWidthException(info, mname, hi, bitWidth(a.tpe))
+ case DoPrim(Head, Seq(a), Seq(n), _) if bitWidth(a.tpe) < n =>
+ errors append new HeadWidthException(info, mname, n, bitWidth(a.tpe))
+ case DoPrim(Tail, Seq(a), Seq(n), _) if bitWidth(a.tpe) <= n =>
+ errors append new TailWidthException(info, mname, n, bitWidth(a.tpe))
case _ =>
}
e map check_width_w(info, mname) map check_width_e(info, mname)
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index a4d9078c..789f2e03 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -38,7 +38,7 @@ import annotation.tailrec
object ConstProp extends Pass {
def name = "Constant Propagation"
- private def pad(e: Expression, t: Type) = (long_BANG(e.tpe), long_BANG(t)) match {
+ private def pad(e: Expression, t: Type) = (bitWidth(e.tpe), bitWidth(t)) match {
case (we, wt) if we < wt => DoPrim(Pad, Seq(e), Seq(wt), t)
case (we, wt) if we == wt => e
}
@@ -62,7 +62,7 @@ object ConstProp extends Pass {
def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
case UIntLiteral(v, w) if v == 0 => UIntLiteral(0, w)
case SIntLiteral(v, w) if v == 0 => UIntLiteral(0, w)
- case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << long_BANG(rhs.tpe).toInt) - 1 => rhs
+ case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << bitWidth(rhs.tpe).toInt) - 1 => rhs
case _ => e
}
}
@@ -72,7 +72,7 @@ object ConstProp extends Pass {
def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
case UIntLiteral(v, _) if v == 0 => rhs
case SIntLiteral(v, _) if v == 0 => asUInt(rhs, e.tpe)
- case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << long_BANG(rhs.tpe).toInt) - 1 => lhs
+ case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << bitWidth(rhs.tpe).toInt) - 1 => lhs
case _ => e
}
}
@@ -89,7 +89,7 @@ object ConstProp extends Pass {
object FoldEqual extends FoldLogicalOp {
def fold(c1: Literal, c2: Literal) = UIntLiteral(if (c1.value == c2.value) 1 else 0, IntWidth(1))
def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
- case UIntLiteral(v, IntWidth(w)) if v == 1 && w == 1 && long_BANG(rhs.tpe) == 1 => rhs
+ case UIntLiteral(v, IntWidth(w)) if v == 1 && w == 1 && bitWidth(rhs.tpe) == 1 => rhs
case _ => e
}
}
@@ -97,7 +97,7 @@ object ConstProp extends Pass {
object FoldNotEqual extends FoldLogicalOp {
def fold(c1: Literal, c2: Literal) = UIntLiteral(if (c1.value != c2.value) 1 else 0, IntWidth(1))
def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
- case UIntLiteral(v, IntWidth(w)) if v == 0 && w == 1 && long_BANG(rhs.tpe) == 1 => rhs
+ case UIntLiteral(v, IntWidth(w)) if v == 0 && w == 1 && bitWidth(rhs.tpe) == 1 => rhs
case _ => e
}
}
@@ -226,7 +226,7 @@ object ConstProp extends Pass {
case Pad => e.args(0) match {
case UIntLiteral(v, _) => UIntLiteral(v, IntWidth(e.consts(0)))
case SIntLiteral(v, _) => SIntLiteral(v, IntWidth(e.consts(0)))
- case _ if long_BANG(e.args(0).tpe) == e.consts(0) => e.args(0)
+ case _ if bitWidth(e.args(0).tpe) == e.consts(0) => e.args(0)
case _ => e
}
case Bits => e.args(0) match {
@@ -234,9 +234,9 @@ object ConstProp extends Pass {
val hi = e.consts(0).toInt
val lo = e.consts(1).toInt
require(hi >= lo)
- UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), width_BANG(e.tpe))
+ UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), getWidth(e.tpe))
}
- case x if long_BANG(e.tpe) == long_BANG(x.tpe) => x.tpe match {
+ case x if bitWidth(e.tpe) == bitWidth(x.tpe) => x.tpe match {
case t: UIntType => x
case _ => asUInt(x, e.tpe)
}
@@ -253,7 +253,7 @@ object ConstProp extends Pass {
private def constPropMux(m: Mux): Expression = (m.tval, m.fval) match {
case _ if m.tval == m.fval => m.tval
case (t: UIntLiteral, f: UIntLiteral) =>
- if (t.value == 1 && f.value == 0 && long_BANG(m.tpe) == 1) m.cond
+ if (t.value == 1 && f.value == 0 && bitWidth(m.tpe) == 1) m.cond
else constPropMuxCond(m)
case _ => constPropMuxCond(m)
}
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 5a81c268..6b2ff6ed 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -214,8 +214,8 @@ object InferWidths extends Pass {
def get_constraints_e(e: Expression): Expression = {
e match {
case (e: Mux) => v ++= Seq(
- WGeq(width_BANG(e.cond), IntWidth(1)),
- WGeq(IntWidth(1), width_BANG(e.cond))
+ WGeq(getWidth(e.cond), IntWidth(1)),
+ WGeq(IntWidth(1), getWidth(e.cond))
)
case _ =>
}
@@ -230,8 +230,8 @@ object InferWidths extends Pass {
val exps = create_exps(s.expr)
v ++= ((locs zip exps).zipWithIndex map {case ((locx, expx), i) =>
get_flip(s.loc.tpe, i, Default) match {
- case Default => WGeq(width_BANG(locx), width_BANG(expx))
- case Flip => WGeq(width_BANG(expx), width_BANG(locx))
+ case Default => WGeq(getWidth(locx), getWidth(expx))
+ case Flip => WGeq(getWidth(expx), getWidth(locx))
}
})
case (s: PartialConnect) =>
@@ -242,17 +242,17 @@ object InferWidths extends Pass {
val locx = locs(x)
val expx = exps(y)
get_flip(s.loc.tpe, x, Default) match {
- case Default => WGeq(width_BANG(locx), width_BANG(expx))
- case Flip => WGeq(width_BANG(expx), width_BANG(locx))
+ case Default => WGeq(getWidth(locx), getWidth(expx))
+ case Flip => WGeq(getWidth(expx), getWidth(locx))
}
})
case (s:DefRegister) => v ++= (Seq(
- WGeq(width_BANG(s.reset), IntWidth(1)),
- WGeq(IntWidth(1), width_BANG(s.reset))
+ WGeq(getWidth(s.reset), IntWidth(1)),
+ WGeq(IntWidth(1), getWidth(s.reset))
) ++ get_constraints_t(s.tpe, s.init.tpe, Default))
case (s:Conditionally) => v ++= Seq(
- WGeq(width_BANG(s.pred), IntWidth(1)),
- WGeq(IntWidth(1), width_BANG(s.pred))
+ WGeq(getWidth(s.pred), IntWidth(1)),
+ WGeq(IntWidth(1), getWidth(s.pred))
)
case _ =>
}
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 798b02da..87033176 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -82,6 +82,14 @@ object toBitMask {
}
}
+object getWidth {
+ def apply(t: Type): Width = t match {
+ case t: GroundType => t.width
+ case _ => error("No width!")
+ }
+ def apply(e: Expression): Width = apply(e.tpe)
+}
+
object bitWidth {
def apply(dt: Type): BigInt = widthOf(dt)
private def widthOf(dt: Type): BigInt = dt match {
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 1a134d11..bef9ac33 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -4,12 +4,11 @@ package passes
import firrtl.ir._
import firrtl.PrimOps._
import firrtl.Mappers._
-import firrtl.Utils.long_BANG
// Makes all implicit width extensions and truncations explicit
object PadWidths extends Pass {
def name = "Pad Widths"
- private def width(t: Type): Int = long_BANG(t).toInt
+ private def width(t: Type): Int = bitWidth(t).toInt
private def width(e: Expression): Int = width(e.tpe)
// Returns an expression with the correct integer width
private def fixup(i: Int)(e: Expression) = {
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-03 05:15:19 +0000