diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 7df3e242..3ba38831 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -325,12 +325,8 @@ class VerilogEmitter extends SeqTransform with Emitter { } def checkCatArgumentLegality(e: Expression): Unit = e match { - case _: UIntLiteral | _: SIntLiteral | _: WRef | _: WSubField => - case DoPrim(Not, args, _,_) => args.foreach(checkArgumentLegality) - case DoPrim(op, args, _,_) if isCast(op) => args.foreach(checkArgumentLegality) - case DoPrim(op, args, _,_) if isBitExtract(op) => args.foreach(checkArgumentLegality) case DoPrim(Cat, args, _, _) => args foreach(checkCatArgumentLegality) - case _ => throw EmitterException(s"Can't emit ${e.getClass.getName} as PrimOp argument") + case _ => checkArgumentLegality(e) } def castCatArgs(a0: Expression, a1: Expression): Seq[Any] = { |