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-rw-r--r--src/main/scala/firrtl/passes/MemUtils.scala80
-rw-r--r--src/main/scala/firrtl/passes/ReplaceMemMacros.scala5
-rw-r--r--src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala63
3 files changed, 77 insertions, 71 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index d2557f8d..1091db5f 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -145,11 +145,27 @@ object createMask {
}
}
-object MemPortUtils {
+object createRef {
+ def apply(n: String, t: Type = UnknownType, k: Kind = ExpKind) = WRef(n, t, k, UNKNOWNGENDER)
+}
+
+object createSubField {
+ def apply(exp: Expression, n: String) = WSubField(exp, n, field_type(exp.tpe, n), UNKNOWNGENDER)
+}
- import AnalysisUtils._
+object connectFields {
+ def apply(lref: Expression, lname: String, rref: Expression, rname: String) =
+ Connect(NoInfo, createSubField(lref, lname), createSubField(rref, rname))
+}
- def flattenType(t: Type) = UIntType(IntWidth(bitWidth(t)))
+object flattenType {
+ def apply(t: Type) = UIntType(IntWidth(bitWidth(t)))
+}
+
+object MemPortUtils {
+ type MemPortMap = collection.mutable.HashMap[String, Expression]
+ type Memories = collection.mutable.ArrayBuffer[DefMemory]
+ type Modules = collection.mutable.ArrayBuffer[DefModule]
def defaultPortSeq(mem: DefMemory) = Seq(
Field("addr", Default, UIntType(IntWidth(ceilLog2(mem.depth) max 1))),
@@ -157,64 +173,10 @@ object MemPortUtils {
Field("clk", Default, ClockType)
)
- def getFillWMask(mem: DefMemory) =
- getInfo(mem.info, "maskGran") match {
- case None => false
- case Some(maskGran) => maskGran == 1
- }
-
- def rPortToBundle(mem: DefMemory) = BundleType(
- defaultPortSeq(mem) :+ Field("data", Flip, mem.dataType))
- def rPortToFlattenBundle(mem: DefMemory) = BundleType(
- defaultPortSeq(mem) :+ Field("data", Flip, flattenType(mem.dataType)))
-
- def wPortToBundle(mem: DefMemory) = BundleType(
- (defaultPortSeq(mem) :+ Field("data", Default, mem.dataType)) ++
- (if (!containsInfo(mem.info, "maskGran")) Nil
- else Seq(Field("mask", Default, createMask(mem.dataType))))
- )
- def wPortToFlattenBundle(mem: DefMemory) = BundleType(
- (defaultPortSeq(mem) :+ Field("data", Default, flattenType(mem.dataType))) ++
- (if (!containsInfo(mem.info, "maskGran")) Nil
- else if (getFillWMask(mem)) Seq(Field("mask", Default, flattenType(mem.dataType)))
- else Seq(Field("mask", Default, flattenType(createMask(mem.dataType)))))
- )
- // TODO: Don't use createMask???
-
- def rwPortToBundle(mem: DefMemory) = BundleType(
- defaultPortSeq(mem) ++ Seq(
- Field("wmode", Default, BoolType),
- Field("wdata", Default, mem.dataType),
- Field("rdata", Flip, mem.dataType)
- ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil
- else Seq(Field("wmask", Default, createMask(mem.dataType)))
- )
- )
-
- def rwPortToFlattenBundle(mem: DefMemory) = BundleType(
- defaultPortSeq(mem) ++ Seq(
- Field("wmode", Default, BoolType),
- Field("wdata", Default, flattenType(mem.dataType)),
- Field("rdata", Flip, flattenType(mem.dataType))
- ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil
- else if (getFillWMask(mem)) Seq(Field("wmask", Default, flattenType(mem.dataType)))
- else Seq(Field("wmask", Default, flattenType(createMask(mem.dataType))))
- )
- )
-
- def memToBundle(s: DefMemory) = BundleType(
- s.readers.map(Field(_, Flip, rPortToBundle(s))) ++
- s.writers.map(Field(_, Flip, wPortToBundle(s))) ++
- s.readwriters.map(Field(_, Flip, rwPortToBundle(s))))
-
- def memToFlattenBundle(s: DefMemory) = BundleType(
- s.readers.map(Field(_, Flip, rPortToFlattenBundle(s))) ++
- s.writers.map(Field(_, Flip, wPortToFlattenBundle(s))) ++
- s.readwriters.map(Field(_, Flip, rwPortToFlattenBundle(s))))
-
// Todo: merge it with memToBundle
def memType(mem: DefMemory) = {
- val rType = rPortToBundle(mem)
+ val rType = BundleType(defaultPortSeq(mem) :+
+ Field("data", Flip, mem.dataType))
val wType = BundleType(defaultPortSeq(mem) ++ Seq(
Field("data", Default, mem.dataType),
Field("mask", Default, createMask(mem.dataType))))
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index 78211cca..33a371a0 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -14,13 +14,12 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
def name = "Replace memories with black box wrappers" +
" (optimizes when write mask isn't needed) + configuration file"
-
// from Albert
def createMemModule(m: DefMemory, wrapperName: String): Seq[DefModule] = {
assert(m.dataType != UnknownType)
- val wrapperIoType = MemPortUtils.memToBundle(m)
+ val wrapperIoType = memToBundle(m)
val wrapperIoPorts = wrapperIoType.fields map (f => Port(NoInfo, f.name, Input, f.tpe))
- val bbIoType = MemPortUtils.memToFlattenBundle(m)
+ val bbIoType = memToFlattenBundle(m)
val bbIoPorts = bbIoType.fields map (f => Port(NoInfo, f.name, Input, f.tpe))
val bbRef = createRef(m.name, bbIoType)
val hasMask = containsInfo(m.info, "maskGran")
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
index 0a685c3c..fbff9bd6 100644
--- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
+++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
@@ -7,20 +7,65 @@ import firrtl.ir._
import firrtl.Utils._
import firrtl.Mappers._
import AnalysisUtils._
+import MemPortUtils._
import MemTransformUtils._
object MemTransformUtils {
+ def getFillWMask(mem: DefMemory) =
+ getInfo(mem.info, "maskGran") match {
+ case None => false
+ case Some(maskGran) => maskGran == 1
+ }
- type MemPortMap = collection.mutable.HashMap[String, Expression]
- type Memories = collection.mutable.ArrayBuffer[DefMemory]
- type Modules = collection.mutable.ArrayBuffer[DefModule]
+ def rPortToBundle(mem: DefMemory) = BundleType(
+ defaultPortSeq(mem) :+ Field("data", Flip, mem.dataType))
+ def rPortToFlattenBundle(mem: DefMemory) = BundleType(
+ defaultPortSeq(mem) :+ Field("data", Flip, flattenType(mem.dataType)))
+
+ def wPortToBundle(mem: DefMemory) = BundleType(
+ (defaultPortSeq(mem) :+ Field("data", Default, mem.dataType)) ++
+ (if (!containsInfo(mem.info, "maskGran")) Nil
+ else Seq(Field("mask", Default, createMask(mem.dataType))))
+ )
+ def wPortToFlattenBundle(mem: DefMemory) = BundleType(
+ (defaultPortSeq(mem) :+ Field("data", Default, flattenType(mem.dataType))) ++
+ (if (!containsInfo(mem.info, "maskGran")) Nil
+ else if (getFillWMask(mem)) Seq(Field("mask", Default, flattenType(mem.dataType)))
+ else Seq(Field("mask", Default, flattenType(createMask(mem.dataType)))))
+ )
+ // TODO: Don't use createMask???
+
+ def rwPortToBundle(mem: DefMemory) = BundleType(
+ defaultPortSeq(mem) ++ Seq(
+ Field("wmode", Default, BoolType),
+ Field("wdata", Default, mem.dataType),
+ Field("rdata", Flip, mem.dataType)
+ ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil
+ else Seq(Field("wmask", Default, createMask(mem.dataType)))
+ )
+ )
+
+ def rwPortToFlattenBundle(mem: DefMemory) = BundleType(
+ defaultPortSeq(mem) ++ Seq(
+ Field("wmode", Default, BoolType),
+ Field("wdata", Default, flattenType(mem.dataType)),
+ Field("rdata", Flip, flattenType(mem.dataType))
+ ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil
+ else if (getFillWMask(mem)) Seq(Field("wmask", Default, flattenType(mem.dataType)))
+ else Seq(Field("wmask", Default, flattenType(createMask(mem.dataType))))
+ )
+ )
+
+ def memToBundle(s: DefMemory) = BundleType(
+ s.readers.map(Field(_, Flip, rPortToBundle(s))) ++
+ s.writers.map(Field(_, Flip, wPortToBundle(s))) ++
+ s.readwriters.map(Field(_, Flip, rwPortToBundle(s))))
+
+ def memToFlattenBundle(s: DefMemory) = BundleType(
+ s.readers.map(Field(_, Flip, rPortToFlattenBundle(s))) ++
+ s.writers.map(Field(_, Flip, wPortToFlattenBundle(s))) ++
+ s.readwriters.map(Field(_, Flip, rwPortToFlattenBundle(s))))
- def createRef(n: String, t: Type = UnknownType, k: Kind = ExpKind) =
- WRef(n, t, k, UNKNOWNGENDER)
- def createSubField(exp: Expression, n: String) =
- WSubField(exp, n, field_type(exp.tpe, n), UNKNOWNGENDER)
- def connectFields(lref: Expression, lname: String, rref: Expression, rname: String) =
- Connect(NoInfo, createSubField(lref, lname), createSubField(rref, rname))
def getMemPortMap(m: DefMemory) = {
val memPortMap = new MemPortMap
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-02 21:52:39 +0000