diff options
Diffstat (limited to 'src')
4 files changed, 49 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala index 31c2a04b..61045c00 100644 --- a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala +++ b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala @@ -106,7 +106,9 @@ class BlackBoxSourceHelper extends firrtl.Transform { file } - BlackBoxSourceHelper.writeFileList(resourceFiles ++ inlineFiles, targetDir) + // Issue #917 - We don't want to list Verilog header files ("*.vh") in our file list - they will automatically be included by reference. + val verilogSourcesOnly = (resourceFiles ++ inlineFiles).filterNot( _.getName().endsWith(".vh")) + BlackBoxSourceHelper.writeFileList(verilogSourcesOnly, targetDir) state } diff --git a/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v b/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v new file mode 100644 index 00000000..fcba38d5 --- /dev/null +++ b/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v @@ -0,0 +1,8 @@ +// See LICENSE for license details. +module ParameterizedViaHeaderAdderExtModule( + input [15:0] foo, + output [15:0] bar +); + `include "VerilogHeaderFile.vh" + assign bar = foo + VALUE; +endmodule diff --git a/src/test/resources/blackboxes/VerilogHeaderFile.vh b/src/test/resources/blackboxes/VerilogHeaderFile.vh new file mode 100644 index 00000000..0844c95f --- /dev/null +++ b/src/test/resources/blackboxes/VerilogHeaderFile.vh @@ -0,0 +1,5 @@ +// See LICENSE for license details. +`ifndef _parameters_vh_ +`define _parameters_vh_ +parameter VALUE = 2; +`endif diff --git a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala index c6918624..b7ecc37a 100644 --- a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala +++ b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala @@ -106,6 +106,39 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec { verilogCompiler.transforms.map { x => x.getClass } should contain (classOf[BlackBoxSourceHelper]) } + "verilog header files" should "be available but not mentioned in the file list" in { + // Issue #917 - We don't want to list Verilog header files ("*.vh") in our file list. + // We don't actually verify that the generated verilog code works, + // we just ensure that the correct files end up where they're expected. + + // We're taking the liberty of recycling the above code with a few minor edits to change the external module name. + val sourceModuleName = "AdderExtModule" + val replacedModuleName = "ParameterizedViaHeaderAdderExtModule" + val pInput = input.replaceAll(sourceModuleName, replacedModuleName) + val pOutput = output.replaceAll(sourceModuleName, replacedModuleName) + + // We'll copy the following resources to the test_run_dir via BlackBoxResourceAnno's + val resourceNames = Seq("ParameterizedViaHeaderAdderExtModule.v", "VerilogHeaderFile.vh") + + val annos = Seq( + BlackBoxTargetDirAnno("test_run_dir")) ++ resourceNames.map{ n => BlackBoxResourceAnno(moduleName, "/blackboxes/" + n)} + + execute(pInput, pOutput, annos) + + // Our resource files should exist in the test_run_dir, + for (n <- resourceNames) + new java.io.File("test_run_dir/" + n).exists should be (true) + + // but our file list should not include the verilog header file. + val fileListFile = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.fileListName}") + fileListFile.exists should be (true) + val fileListFileSource = io.Source.fromFile(fileListFile) + val fileList = fileListFileSource.getLines.mkString + fileListFileSource.close() + fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be (true) + fileList.contains("VerilogHeaderFile.vh") should be (false) + } + behavior of "BlackBox resources that do not exist" it should "provide a useful error message for BlackBoxResourceAnno" in { |