aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Driver.scala1
-rw-r--r--src/main/scala/firrtl/RenameMap.scala2
-rw-r--r--src/main/scala/firrtl/constraint/ConstraintSolver.scala1
-rw-r--r--src/main/scala/firrtl/ir/IR.scala1
-rw-r--r--src/main/scala/firrtl/passes/Checks.scala3
-rw-r--r--src/main/scala/firrtl/passes/TrimIntervals.scala4
-rw-r--r--src/main/scala/firrtl/stage/FirrtlStage.scala3
-rw-r--r--src/main/scala/firrtl/transforms/SimplifyMems.scala1
8 files changed, 3 insertions, 13 deletions
diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 642e7f3f..babcd406 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -14,7 +14,6 @@ import firrtl.stage.{FirrtlExecutionResultView, FirrtlStage}
import firrtl.stage.phases.DriverCompatibility
import firrtl.options.{StageUtils, Phase, Viewer}
import firrtl.options.phases.DeletedWrapper
-import firrtl.FileUtils
/**
diff --git a/src/main/scala/firrtl/RenameMap.scala b/src/main/scala/firrtl/RenameMap.scala
index 825b0098..03f01991 100644
--- a/src/main/scala/firrtl/RenameMap.scala
+++ b/src/main/scala/firrtl/RenameMap.scala
@@ -3,7 +3,7 @@
package firrtl
import annotations._
-import firrtl.RenameMap.{CircularRenameException, IllegalRenameException}
+import firrtl.RenameMap.IllegalRenameException
import firrtl.annotations.TargetToken.{Field, Index, Instance, OfModule}
import scala.collection.mutable
diff --git a/src/main/scala/firrtl/constraint/ConstraintSolver.scala b/src/main/scala/firrtl/constraint/ConstraintSolver.scala
index 52440b15..40fff728 100644
--- a/src/main/scala/firrtl/constraint/ConstraintSolver.scala
+++ b/src/main/scala/firrtl/constraint/ConstraintSolver.scala
@@ -5,7 +5,6 @@ package firrtl.constraint
import firrtl._
import firrtl.ir._
import firrtl.Utils.throwInternalError
-import firrtl.annotations.ReferenceTarget
import scala.collection.mutable
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index 63c620d1..07cbb7e2 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -7,7 +7,6 @@ import Utils.{dec2string, indent, trim}
import firrtl.constraint.{Constraint, IsKnown, IsVar}
import scala.math.BigDecimal.RoundingMode._
-import scala.collection.mutable
/** Intermediate Representation */
abstract class FirrtlNode {
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 4239247c..06a3368b 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -142,7 +142,7 @@ trait CheckHighFormLike {
t match {
case tx: VectorType if tx.size < 0 =>
errors.append(new NegVecSizeException(info, mname))
- case i: IntervalType => i
+ case _: IntervalType =>
case _ => t foreach checkHighFormW(info, mname)
}
}
@@ -151,7 +151,6 @@ trait CheckHighFormLike {
e match {
case _: Reference | _: SubField | _: SubIndex | _: SubAccess => // No error
case _: WRef | _: WSubField | _: WSubIndex | _: WSubAccess | _: Mux | _: ValidIf => // No error
- case _: Reference | _: SubField | _: SubIndex | _: SubAccess => // No error
case _ => errors.append(new InvalidAccessException(info, mname))
}
}
diff --git a/src/main/scala/firrtl/passes/TrimIntervals.scala b/src/main/scala/firrtl/passes/TrimIntervals.scala
index dec64ee7..f659815e 100644
--- a/src/main/scala/firrtl/passes/TrimIntervals.scala
+++ b/src/main/scala/firrtl/passes/TrimIntervals.scala
@@ -2,13 +2,9 @@
package firrtl.passes
-import scala.collection.mutable
import firrtl.PrimOps._
import firrtl.ir._
-import firrtl._
import firrtl.Mappers._
-import firrtl.Utils.{error, field_type, getUIntWidth, max, module_type, sub_type}
-import Implicits.{bigint2WInt, int2WInt}
import firrtl.constraint.{IsFloor, IsKnown, IsMul}
/** Replaces IntervalType with SIntType, three AST walks:
diff --git a/src/main/scala/firrtl/stage/FirrtlStage.scala b/src/main/scala/firrtl/stage/FirrtlStage.scala
index 92b461a1..2f7f0d11 100644
--- a/src/main/scala/firrtl/stage/FirrtlStage.scala
+++ b/src/main/scala/firrtl/stage/FirrtlStage.scala
@@ -4,9 +4,8 @@ package firrtl.stage
import firrtl.{AnnotationSeq, CustomTransformException, FirrtlInternalException,
FirrtlUserException, FIRRTLException, Utils}
-import firrtl.options.{Stage, Phase, PhaseException, Shell, OptionsException, StageMain, StageUtils}
+import firrtl.options.{Stage, Phase, PhaseException, Shell, OptionsException, StageMain}
import firrtl.options.phases.DeletedWrapper
-import firrtl.passes.{PassException, PassExceptions}
import scala.util.control.ControlThrowable
diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala
index 140efc9f..1552f2f6 100644
--- a/src/main/scala/firrtl/transforms/SimplifyMems.scala
+++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala
@@ -10,7 +10,6 @@ import firrtl.passes._
import firrtl.passes.memlib._
import scala.collection.mutable
-import Utils._
import AnalysisUtils._
import MemPortUtils._
import ResolveMaskGranularity._