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-rw-r--r--src/main/antlr4/FIRRTL.g448
-rw-r--r--src/main/scala/firrtl/Driver.scala25
-rw-r--r--src/main/scala/firrtl/IR.scala6
-rw-r--r--src/main/scala/firrtl/Parser.scala11
-rw-r--r--src/main/scala/firrtl/Serialize.scala43
-rw-r--r--src/main/scala/firrtl/Translator.scala9
-rw-r--r--src/main/scala/firrtl/Visitor.scala57
-rw-r--r--src/test/scala/firrtlTests/CheckInitializationSpec.scala3
-rw-r--r--src/test/scala/firrtlTests/CheckSpec.scala2
-rw-r--r--src/test/scala/firrtlTests/ChirrtlSpec.scala2
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala3
-rw-r--r--src/test/scala/firrtlTests/LowerTypesSpec.scala2
-rw-r--r--src/test/scala/firrtlTests/UniquifySpec.scala2
-rw-r--r--src/test/scala/firrtlTests/UnitTests.scala9
14 files changed, 134 insertions, 88 deletions
diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index 5daf20ae..c452fae1 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -37,16 +37,16 @@ grammar FIRRTL;
// Does there have to be at least one module?
circuit
- : 'circuit' id ':' '{' module* '}'
+ : 'circuit' id ':' info? '{' module* '}'
;
module
- : 'module' id ':' '{' port* block '}'
- | 'extmodule' id ':' '{' port* '}'
+ : 'module' id ':' info? '{' port* block '}'
+ | 'extmodule' id ':' info? '{' port* '}'
;
port
- : dir id ':' type
+ : dir id ':' type info?
;
dir
@@ -72,30 +72,35 @@ block
;
stmt
- : 'wire' id ':' type
- | 'reg' id ':' type exp ('with' ':' '{' 'reset' '=>' '(' exp exp ')' '}')?
- | 'mem' id ':' '{' ( 'data-type' '=>' type
+ : 'wire' id ':' type info?
+ | 'reg' id ':' type exp ('with' ':' '{' 'reset' '=>' '(' exp exp ')' '}')? info?
+ | 'mem' id ':' info? '{'
+ ( 'data-type' '=>' type
| 'depth' '=>' IntLit
| 'read-latency' '=>' IntLit
| 'write-latency' '=>' IntLit
| 'read-under-write' '=>' ruw
| 'reader' '=>' id
| 'writer' '=>' id
- | 'readwriter' '=>' id
+ | 'readwriter' '=>' id
)*
'}'
- | 'cmem' id ':' type
- | 'smem' id ':' type
- | mdir 'mport' id '=' id '[' exp ']' exp
- | 'inst' id 'of' id
- | 'node' id '=' exp
- | exp '<=' exp
- | exp '<-' exp
- | exp 'is' 'invalid'
- | 'when' exp ':' '{' block '}' ( 'else' ':' '{' block '}' )?
- | 'stop(' exp exp IntLit ')'
- | 'printf(' exp exp StringLit (exp)* ')'
- | 'skip'
+ | 'cmem' id ':' type info?
+ | 'smem' id ':' type info?
+ | mdir 'mport' id '=' id '[' exp ']' exp info?
+ | 'inst' id 'of' id info?
+ | 'node' id '=' exp info?
+ | exp '<=' exp info?
+ | exp '<-' exp info?
+ | exp 'is' 'invalid' info?
+ | 'when' exp ':' info? '{' block '}' ( 'else' ':' '{' block '}' )?
+ | 'stop(' exp exp IntLit ')' info?
+ | 'printf(' exp exp StringLit (exp)* ')' info?
+ | 'skip' info?
+ ;
+
+info
+ : FileInfo
;
mdir
@@ -245,6 +250,9 @@ StringLit
: '"' ('\\"'|.)*? '"'
;
+FileInfo
+ : '@[' ('\\]'|.)*? ']'
+ ;
Id
: IdNondigit
diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 94e24bf8..587be24c 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -35,20 +35,23 @@ import scala.sys.process._
import com.typesafe.scalalogging.LazyLogging
import Utils._
+import Parser.{InfoMode, IgnoreInfo, UseInfo, GenInfo, AppendInfo}
object Driver extends LazyLogging {
private val usage = """
Usage: sbt "run-main firrtl.Driver -i <input_file> -o <output_file> -X <compiler>"
- firrtl -i <input_file> -o <output_file> -X <compiler>
+ firrtl -i <input_file> -o <output_file> -X <compiler> [options]
Options:
- -X <compiler> Specify the target language
- Currently supported: verilog firrtl
+ -X <compiler> Specify the target language
+ Currently supported: verilog firrtl
+ --info-mode=<mode> Specify Info Mode
+ Supported modes: ignore, use, gen, append
"""
private val defaultOptions = Map[Symbol, Any]().withDefaultValue(false)
- def compile(input: String, output: String, compiler: Compiler)
+ def compile(input: String, output: String, compiler: Compiler, infoMode: InfoMode = IgnoreInfo)
{
- val parsedInput = Parser.parse(input, Source.fromFile(input).getLines)
+ val parsedInput = Parser.parse(Source.fromFile(input).getLines, infoMode)
val writerOutput = new PrintWriter(new File(output))
compiler.run(parsedInput, writerOutput)
writerOutput.close
@@ -68,6 +71,8 @@ Options:
nextOption(map ++ Map('input -> value), tail)
case "-o" :: value :: tail =>
nextOption(map ++ Map('output -> value), tail)
+ case "--info-mode" :: value :: tail =>
+ nextOption(map ++ Map('infoMode -> value), tail)
case ("-h" | "--help") :: tail =>
nextOption(map ++ Map('help -> true), tail)
case option :: tail =>
@@ -89,10 +94,16 @@ Options:
case s: String => s
case false => throw new Exception("No output file provided!" + usage)
}
+ val infoMode = options('infoMode) match {
+ case ("use" | false) => UseInfo
+ case "ignore" => IgnoreInfo
+ case "gen" => GenInfo(input)
+ case "append" => AppendInfo(input)
+ }
options('compiler) match {
- case "verilog" => compile(input, output, VerilogCompiler)
- case "firrtl" => compile(input, output, FIRRTLCompiler)
+ case "verilog" => compile(input, output, VerilogCompiler, infoMode)
+ case "firrtl" => compile(input, output, FIRRTLCompiler, infoMode)
case other => throw new Exception("Invalid compiler! " + other)
}
}
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 66a00229..c762b198 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -36,10 +36,10 @@ Member of most Stmt case classes.
*/
trait Info
case object NoInfo extends Info {
- override def toString(): String = "NoFileInfo"
+ override def toString(): String = ""
}
-case class FileInfo(file: String, line: Int, column: Int) extends Info {
- override def toString(): String = s"$file@$line.$column"
+case class FileInfo(info: StringLit) extends Info {
+ override def toString(): String = " @[" + info.serialize + "]"
}
class FIRRTLException(str: String) extends Exception(str)
diff --git a/src/main/scala/firrtl/Parser.scala b/src/main/scala/firrtl/Parser.scala
index 070a3619..e6489b2f 100644
--- a/src/main/scala/firrtl/Parser.scala
+++ b/src/main/scala/firrtl/Parser.scala
@@ -41,7 +41,7 @@ case class InvalidEscapeCharException(message: String) extends ParserException(m
object Parser extends LazyLogging
{
/** Takes Iterator over lines of FIRRTL, returns AST (root node is Circuit) */
- def parse(filename: String, lines: Iterator[String], useInfo: Boolean = true): Circuit = {
+ def parse(lines: Iterator[String], infoMode: InfoMode = UseInfo): Circuit = {
val fixedInput = time("Translator") { Translator.addBrackets(lines) }
val antlrStream = new ANTLRInputStream(fixedInput.result)
val lexer = new FIRRTLLexer(antlrStream)
@@ -56,7 +56,7 @@ object Parser extends LazyLogging
val numSyntaxErrors = parser.getNumberOfSyntaxErrors
if (numSyntaxErrors > 0) throw new ParserException(s"${numSyntaxErrors} syntax error(s) detected")
- val visitor = new Visitor(filename, useInfo)
+ val visitor = new Visitor(infoMode)
val ast = time("Visitor") { visitor.visit(cst) } match {
case c: Circuit => c
case x => throw new ClassCastException("Error! AST not rooted with Circuit node!")
@@ -65,6 +65,11 @@ object Parser extends LazyLogging
ast
}
- def parse(lines: Seq[String]): Circuit = parse("<None>", lines.iterator)
+ def parse(lines: Seq[String]): Circuit = parse(lines.iterator)
+ sealed abstract class InfoMode
+ case object IgnoreInfo extends InfoMode
+ case object UseInfo extends InfoMode
+ case class GenInfo(filename: String) extends InfoMode
+ case class AppendInfo(filename: String) extends InfoMode
}
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index 7419dbbf..0229bb57 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -54,6 +54,8 @@ private object Serialize {
if (bi < BigInt(0)) "\"h" + bi.toString(16).substring(1) + "\""
else "\"h" + bi.toString(16) + "\""
+ def serialize(info: Info): String = " " + info.toString
+
def serialize(op: PrimOp): String = op.getString
def serialize(lit: StringLit): String = FIRRTLStringLitHandler.escape(lit)
@@ -80,17 +82,17 @@ private object Serialize {
def serialize(stmt: Stmt): String = {
stmt match {
- case w: DefWire => s"wire ${w.name} : ${serialize(w.tpe)}"
+ case w: DefWire => s"wire ${w.name} : ${serialize(w.tpe)}${w.info}"
case r: DefRegister =>
- val str = new StringBuilder(s"reg ${r.name} : ${serialize(r.tpe)}, ${serialize(r.clock)} with : ")
+ val str = new StringBuilder(s"reg ${r.name} : ${serialize(r.tpe)}, ${serialize(r.clock)} with :")
withIndent {
- str ++= newline + s"reset => (${serialize(r.reset)}, ${serialize(r.init)})"
+ str ++= newline + s"reset => (${serialize(r.reset)}, ${serialize(r.init)})${r.info}"
}
str.toString
- case i: DefInstance => s"inst ${i.name} of ${i.module}"
- case i: WDefInstance => s"inst ${i.name} of ${i.module}"
+ case i: DefInstance => s"inst ${i.name} of ${i.module}${i.info}"
+ case i: WDefInstance => s"inst ${i.name} of ${i.module}${i.info}"
case m: DefMemory => {
- val str = new StringBuilder(s"mem ${m.name} : ")
+ val str = new StringBuilder(s"mem ${m.name} :${m.info}")
withIndent {
str ++= newline +
s"data-type => ${serialize(m.data_type)}" + newline +
@@ -107,11 +109,11 @@ private object Serialize {
}
str.result
}
- case n: DefNode => s"node ${n.name} = ${serialize(n.value)}"
- case c: Connect => s"${serialize(c.loc)} <= ${serialize(c.exp)}"
- case b: BulkConnect => s"${serialize(b.loc)} <- ${serialize(b.exp)}"
+ case n: DefNode => s"node ${n.name} = ${serialize(n.value)}${n.info}"
+ case c: Connect => s"${serialize(c.loc)} <= ${serialize(c.exp)}${c.info}"
+ case b: BulkConnect => s"${serialize(b.loc)} <- ${serialize(b.exp)}${b.info}"
case w: Conditionally => {
- var str = new StringBuilder(s"when ${serialize(w.pred)} : ")
+ var str = new StringBuilder(s"when ${serialize(w.pred)} :${w.info}")
withIndent { str ++= newline + serialize(w.conseq) }
w.alt match {
case s:Empty => str.result
@@ -130,17 +132,18 @@ private object Serialize {
}
s.result
}
- case i: IsInvalid => s"${serialize(i.exp)} is invalid"
- case s: Stop => s"stop(${serialize(s.clk)}, ${serialize(s.en)}, ${s.ret})"
+ case i: IsInvalid => s"${serialize(i.exp)} is invalid${i.info}"
+ case s: Stop => s"stop(${serialize(s.clk)}, ${serialize(s.en)}, ${s.ret})${s.info}"
case p: Print => {
val q = '"'.toString
s"printf(${serialize(p.clk)}, ${serialize(p.en)}, ${q}${serialize(p.string)}${q}" +
- (if (p.args.nonEmpty) p.args.map(serialize).mkString(", ", ", ", "") else "") + ")"
+ (if (p.args.nonEmpty) p.args.map(serialize).mkString(", ", ", ", "") else "") +
+ s")${p.info}"
}
case s: Empty => "skip"
case s: CDefMemory => {
- if (s.seq) s"smem ${s.name} : ${serialize(s.tpe)} [${s.size}]"
- else s"cmem ${s.name} : ${serialize(s.tpe)} [${s.size}]"
+ if (s.seq) s"smem ${s.name} : ${serialize(s.tpe)} [${s.size}]${s.info}"
+ else s"cmem ${s.name} : ${serialize(s.tpe)} [${s.size}]${s.info}"
}
case s: CDefMPort => {
val dir = s.direction match {
@@ -149,7 +152,7 @@ private object Serialize {
case MWrite => "write"
case MReadWrite => "rdwr"
}
- s"${dir} mport ${s.name} = ${s.mem}[${serialize(s.exps(0))}], ${serialize(s.exps(1))}"
+ s"${dir} mport ${s.name} = ${s.mem}[${serialize(s.exps(0))}], ${serialize(s.exps(1))}${s.info}"
}
}
}
@@ -192,12 +195,12 @@ private object Serialize {
}
def serialize(p: Port): String =
- s"${serialize(p.direction)} ${p.name} : ${serialize(p.tpe)}"
+ s"${serialize(p.direction)} ${p.name} : ${serialize(p.tpe)}${p.info}"
def serialize(m: Module): String = {
m match {
case m: InModule => {
- var s = new StringBuilder(s"module ${m.name} : ")
+ var s = new StringBuilder(s"module ${m.name} :${m.info}")
withIndent {
s ++= m.ports.map(newline ++ serialize(_)).mkString
s ++= newline ++ serialize(m.body)
@@ -205,7 +208,7 @@ private object Serialize {
s.toString
}
case m: ExModule => {
- var s = new StringBuilder(s"extmodule ${m.name} : ")
+ var s = new StringBuilder(s"extmodule ${m.name} :${m.info}")
withIndent {
s ++= m.ports.map(newline ++ serialize(_)).mkString
s ++= newline
@@ -216,7 +219,7 @@ private object Serialize {
}
def serialize(c: Circuit): String = {
- var s = new StringBuilder(s"circuit ${c.main} : ")
+ var s = new StringBuilder(s"circuit ${c.main} :${c.info}")
withIndent { s ++= newline ++ c.modules.map(serialize).mkString(newline + newline) }
s ++= newline ++ newline
s.toString
diff --git a/src/main/scala/firrtl/Translator.scala b/src/main/scala/firrtl/Translator.scala
index 0fcc84b8..4b0bd1e7 100644
--- a/src/main/scala/firrtl/Translator.scala
+++ b/src/main/scala/firrtl/Translator.scala
@@ -66,10 +66,11 @@ object Translator
}
s.take(i)
}
+ def extractFileInfo(str: String): (String, String) = str span (_ != '@')
val scopers = """(circuit|module|when|else|mem|with)"""
val MultiLineScope = ("""(.*""" + scopers + """)(.*:\s*)""").r
- val OneLineScope = ("""(.*""" + scopers + """\s*:\s*)\((.*)\)\s*""").r
+ val OneLineScope = ("""(.*(with)\s*:\s*)\((.*)\)\s*""").r
// Function start
val it = inputIt.zipWithIndex
@@ -95,6 +96,7 @@ object Translator
while( it.hasNext ) {
it.next match { case (lineText, lineNum) =>
val text = stripComments(lineText)
+ val (code, fileInfo) = extractFileInfo(text)
val spaces = countSpaces(text)
val l = if (text.length > spaces ) { // Check that line has text in it
@@ -118,14 +120,13 @@ object Translator
throw new Exception("Invalid increase in scope on line " + lineNum)
// Now match on legal scope increasers
- text match {
+ code match {
case OneLineScope(head, keyword, body) => {
newScope = false
- head + "{" + body + "}"
+ head + "{" + body + "} " + fileInfo
}
case MultiLineScope(head, keyword, tail) => {
newScope = true
- //text.replaceFirst(":", ": {")
text + " { "
}
case _ => {
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 1c47508d..f2a3953b 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -41,16 +41,14 @@ import scala.collection.JavaConversions._
import antlr._
import PrimOps._
import FIRRTLParser._
+import Parser.{InfoMode, IgnoreInfo, UseInfo, GenInfo, AppendInfo}
import scala.annotation.tailrec
-class Visitor(val fullFilename: String, val useInfo : Boolean) extends FIRRTLBaseVisitor[AST]
+class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
{
// Strip file path
- private val filename = fullFilename.drop(fullFilename.lastIndexOf("/")+1)
+ private def stripPath(filename: String) = filename.drop(filename.lastIndexOf("/")+1)
- // For some reason visitCircuit does not visit the right function
- // FIXME for some reason this cannot be private, probably because it extends
- // FIRRTLBaseVisitor which is in a subpackage?
def visit[AST](ctx: FIRRTLParser.CircuitContext): Circuit = visitCircuit(ctx)
// These regex have to change if grammar changes
@@ -77,22 +75,40 @@ class Visitor(val fullFilename: String, val useInfo : Boolean) extends FIRRTLBas
}
}
private def string2Int(s: String): Int = string2BigInt(s).toInt
- private def getInfo(ctx: ParserRuleContext): Info =
- if (useInfo) {
- FileInfo(filename, ctx.getStart().getLine(), ctx.getStart().getCharPositionInLine())
- } else NoInfo
- private def visitCircuit[AST](ctx: FIRRTLParser.CircuitContext): Circuit =
- Circuit(getInfo(ctx), ctx.module.map(visitModule), (ctx.id.getText))
+ private def visitInfo(ctx: Option[FIRRTLParser.InfoContext], parentCtx: ParserRuleContext): Info = {
+ def genInfo(filename: String): String =
+ stripPath(filename) + "@" + parentCtx.getStart.getLine + "." +
+ parentCtx.getStart.getCharPositionInLine
+ lazy val useInfo: String = ctx match {
+ case Some(info) => info.getText.drop(2).init // remove surrounding @[ ... ]
+ case None => ""
+ }
+ infoMode match {
+ case UseInfo =>
+ if (useInfo.length == 0) NoInfo else FileInfo(FIRRTLStringLitHandler.unescape(useInfo))
+ case AppendInfo(filename) =>
+ val newInfo = useInfo + ":" + genInfo(filename)
+ FileInfo(FIRRTLStringLitHandler.unescape(newInfo))
+ case GenInfo(filename) => FileInfo(FIRRTLStringLitHandler.unescape(genInfo(filename)))
+ case IgnoreInfo => NoInfo
+ }
+ }
+
+ private def visitCircuit[AST](ctx: FIRRTLParser.CircuitContext): Circuit =
+ Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.map(visitModule), (ctx.id.getText))
- private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module =
- ctx.getChild(0).getText match {
- case "module" => InModule(getInfo(ctx), (ctx.id.getText), ctx.port.map(visitPort), visitBlock(ctx.block))
- case "extmodule" => ExModule(getInfo(ctx), (ctx.id.getText), ctx.port.map(visitPort))
- }
+ private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module = {
+ val info = visitInfo(Option(ctx.info), ctx)
+ ctx.getChild(0).getText match {
+ case "module" => InModule(info, ctx.id.getText, ctx.port.map(visitPort), visitBlock(ctx.block))
+ case "extmodule" => ExModule(info, ctx.id.getText, ctx.port.map(visitPort))
+ }
+ }
- private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port =
- Port(getInfo(ctx), (ctx.id.getText), visitDir(ctx.dir), visitType(ctx.`type`))
+ private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port = {
+ Port(visitInfo(Option(ctx.info), ctx), (ctx.id.getText), visitDir(ctx.dir), visitType(ctx.`type`))
+ }
private def visitDir[AST](ctx: FIRRTLParser.DirContext): Direction =
ctx.getText match {
case "input" => INPUT
@@ -150,7 +166,7 @@ class Visitor(val fullFilename: String, val useInfo : Boolean) extends FIRRTLBas
}
}
- val info = getInfo(ctx)
+ val info = visitInfo(Option(ctx.info), ctx)
// Build map of different Memory fields to their values
val map = try {
parseChildren(ctx.children.drop(4), Map[String, Seq[ParseTree]]()) // First 4 tokens are 'mem' id ':' '{', skip to fields
@@ -177,8 +193,7 @@ class Visitor(val fullFilename: String, val useInfo : Boolean) extends FIRRTLBas
// visitStmt
private def visitStmt[AST](ctx: FIRRTLParser.StmtContext): Stmt = {
- val info = getInfo(ctx)
-
+ val info = visitInfo(Option(ctx.info), ctx)
ctx.getChild(0) match {
case term: TerminalNode => term.getText match {
case "wire" => DefWire(info, (ctx.id(0).getText), visitType(ctx.`type`(0)))
diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index 58477e07..49d5bc08 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -31,10 +31,11 @@ import java.io._
import org.scalatest._
import org.scalatest.prop._
import firrtl._
+import firrtl.Parser.IgnoreInfo
import firrtl.passes._
class CheckInitializationSpec extends FirrtlFlatSpec {
- private def parse(input: String) = Parser.parse("", input.split("\n").toIterator, false)
+ private def parse(input: String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
private val passes = Seq(
ToWorkingIR,
CheckHighForm,
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 4a646c38..ea0767bb 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -20,7 +20,7 @@ class CheckSpec extends FlatSpec with Matchers {
| read-latency => 0
| write-latency => 1""".stripMargin
intercept[PassExceptions] {
- passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+ passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
}
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index dd2b7e31..0059d7ed 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -67,7 +67,7 @@ class ChirrtlSpec extends FirrtlFlatSpec {
| infer mport y = ram[UInt(4)], newClock
| y <= UInt(5)
""".stripMargin
- passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+ passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
}
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 5f5705d9..cfcb7f45 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -3,6 +3,7 @@ package firrtlTests
import org.scalatest.Matchers
import java.io.{StringWriter,Writer}
import firrtl._
+import firrtl.Parser.IgnoreInfo
import firrtl.passes._
// Tests the following cases for constant propagation:
@@ -20,7 +21,7 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
ResolveGenders,
InferWidths,
ConstProp)
- def parse(input: String): Circuit = Parser.parse("", input.split("\n").toIterator, false)
+ def parse(input: String): Circuit = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
private def exec (input: String) = {
passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index 8da10b3a..736849f5 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -32,7 +32,7 @@ class LowerTypesSpec extends FirrtlFlatSpec {
LowerTypes)
private def executeTest(input: String, expected: Seq[String]) = {
- val c = passes.foldLeft(Parser.parse("", input.split("\n").toIterator)) {
+ val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
val lines = c.serialize.split("\n") map normalized
diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala
index 7e01c3eb..71f41074 100644
--- a/src/test/scala/firrtlTests/UniquifySpec.scala
+++ b/src/test/scala/firrtlTests/UniquifySpec.scala
@@ -44,7 +44,7 @@ class UniquifySpec extends FirrtlFlatSpec {
)
private def executeTest(input: String, expected: Seq[String]) = {
- val c = passes.foldLeft(Parser.parse("", input.split("\n").toIterator)) {
+ val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
val lines = c.serialize.split("\n") map normalized
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 7276aabb..cee2c15d 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -32,11 +32,12 @@ import org.scalatest._
import org.scalatest.prop._
import firrtl._
import firrtl.passes._
+import firrtl.Parser.IgnoreInfo
class UnitTests extends FirrtlFlatSpec {
- def parse (input:String) = Parser.parse("",input.split("\n").toIterator,false)
+ def parse (input:String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
- val c = passes.foldLeft(Parser.parse("", input.split("\n").toIterator)) {
+ val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
val lines = c.serialize.split("\n") map normalized
@@ -132,7 +133,7 @@ class UnitTests extends FirrtlFlatSpec {
ToWorkingIR,
InferTypes)
intercept[PassException] {
- val c = Parser.parse("",splitExpTestCode.split("\n").toIterator)
+ val c = Parser.parse(splitExpTestCode.split("\n").toIterator)
val c2 = passes.foldLeft(c)((c, p) => p run c)
new VerilogEmitter().run(c2, new OutputStreamWriter(new ByteArrayOutputStream))
}
@@ -143,7 +144,7 @@ class UnitTests extends FirrtlFlatSpec {
ToWorkingIR,
SplitExpressions,
InferTypes)
- val c = Parser.parse("",splitExpTestCode.split("\n").toIterator)
+ val c = Parser.parse(splitExpTestCode.split("\n").toIterator)
val c2 = passes.foldLeft(c)((c, p) => p run c)
new VerilogEmitter().run(c2, new OutputStreamWriter(new ByteArrayOutputStream))
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 10:12:58 +0000